Memory devices for pattern matching

Patent metadata

Field	Value
Publication number	US-10089359-B2
Application number	US-201615253965-A
Country	US
Kind code	B2
Filing date	Sep 1, 2016
Priority date	Apr 18, 2011
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

First claim

What is claimed is:

1. A memory device, comprising:
an array of memory cells;
a controller;
a plurality of key registers to store a representation of a key word to be searched; and
a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells;
wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;
wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;
wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and
wherein the memory device is further configured to determine an error count by:
precharging a selected data line of a string of memory cells of the array of memory cells;
sensing on the selected data line;
if the selected data line does not discharge, storing an error count value of zero;
if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges;
if the data line does not discharge, storing an error count value equal to the reference current level; and
if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and
storing an error count based on the reference current at which the data line remains charged.

2. The memory device of claim 1 , wherein the memory device is further configured to compare selected programmed bits of the key word to data stored in the array of memory cells.

3. The memory device of claim 1 , wherein each bit of the key word is programmed into two bits of a respected one of the plurality of key registers that correspond to gate voltages to be applied to gates of two respective memory cells of the stored data.

4. The memory device of claim 3 , wherein the memory device is further configured to apply the programmed gate voltages of a selected bit of the key word to be searched to control gates of the two respective memory cells of the stored data.

5. The memory device of claim 1 , wherein the memory device is further configured to indicate a match when a precharged data line connected to a string of memory cells containing the two respective memory cells does not discharge on sensing.

6. The memory device of claim 1 , wherein the memory device is further configured to indicate a non-match when a precharged data line connected to a string of memory cells containing the memory cells discharges on sensing.

7. A memory device, comprising:
an array of memory cells;
a controller;
a plurality of key registers to store a representation of a key word to be searched; and
a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit of the key word from a key register of the plurality of key registers to compare to data stored in the array of memory cells;
wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;
wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;
wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells; and
wherein each multiplexer of the plurality of multiplexers is configured to:
receive a plurality of voltage levels;
apply a first voltage level of the plurality of voltage levels to one access line of a corresponding string of memory cells of the array of memory cells when the bit of the key word has a first value;
apply a second voltage level of the plurality of voltage levels to the one access line of the corresponding string of memory cells when the bit of the key word has a second value different than the first value;
apply the second voltage level to an other access line of the corresponding string of memory cells when the bit of the key word has the first value;
apply the first voltage level to the other access line of the corresponding string of memory cells when the bit of the key word has the second value; and
apply a particular voltage level of the plurality of voltage levels to remaining access lines of the corresponding string of memory cells regardless of the value of the bit of the key word; and

wherein the memory device is further configured to determine an error count by:
precharging a selected data line of a string of memory cells of the array of memory cells;
sensing on the selected data line;
if the selected data line does not discharge, storing an error count value of zero;
if the selected data line discharges, precharging the selected data line, applying a reference current to the selected data line at a first level sufficient to overcome a single bit non-match in the string, and sensing to determine if the data line discharges;
if the data line does not discharge, storing an error count value equal to the reference current level; and
if the data line discharges, incrementing the reference current to a next level sufficient to overcome an additional bit non-match in the string, precharging the data line, sensing, and if the data line discharges, repeating until a maximum reference current is reached or the data line stays charged; and
storing an error count based on the reference current at which the data line remains charged.

8. The memory device of claim 7 , wherein each access line of the corresponding string of memory cells is coupled to a control gate of a memory cell of the corresponding string of memory cells.

9. The memory device of claim 8 , wherein the particular voltage level is configured to activate a memory cell of the corresponding string of memory cells regardless of a data value of that memory cell.

10. The memory device of claim 7 , wherein each multiplexer of the plurality of multiplexers is configured to receive the same plurality of voltage levels.

11. The memory device of claim 7 , wherein the particular voltage level is selected from a group consisting of the first voltage level and the second voltage level.

12. A memory device, comprising:
an array of memory cells;
a controller;
a plurality of key registers to store a representation of a key word to be searched; and
a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit of the key word from a corresponding key register of the plurality of key registers to compare to data stored in the array of memory cells;
wherein the controller is configured to program the key word to be searched into the plurality of key registers of the memory device, each bit of the key word associated with two separate register entries;
wherein the memory device is configured to pattern check for the key word to be searched in the array of memory cells;
wherein each bit of data stored in the array of memory cells to be pattern checked is stored in two memory cells of the array of memory cells;
wherein each multiplexer o

Assignees

• Micron Technology Inc

Inventors

• De Santis Luca
• Marotta Giulio G
• Tiburzi Marco-Domenico
• Vali Tommaso
• Roohparvar Frankie F
• Macerola Agostino

Classifications

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F12/0802

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G11C29/50016

  of retention · CPC title

• G11C15/046

  using non-volatile storage elements · CPC title

• G06F3/0628

  making use of a particular technique · CPC title