Watchdog timer

Patent metadata

Field	Value
Publication number	US-10089164-B2
Application number	US-201615053504-A
Country	US
Kind code	B2
Filing date	Feb 25, 2016
Priority date	Feb 27, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

A microcontroller may comprise a central processing unit coupled with a plurality of peripheral devices through a system bus; and a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further having logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer.

First claim

The invention claimed is:

1. A watchdog timer unit configured to define a first and a second watchdog time period, wherein the watchdog timer unit comprises a clock input receiving a first and a second clock signal, a watchdog timer and a clock selection unit which is controlled, after activation of the watchdog timer unit, to automatically select the first to clock the watchdog timer until a first clear watchdog signal has been received whereupon the watchdog timer is reset and the clock selection unit selects the second clock signal to clock the timer, wherein the first watchdog time period is set to be longer than the second watchdog time period, and wherein the first watchdog time period is defined by the first clock signal fed to the watchdog timer unit and the second watchdog time period is defined by the second clock signal fed to the watchdog timer unit.

2. The watchdog timer unit according to claim 1 , wherein the watchdog timer comprises a first timer receiving the first clock signal and a second timer receiving the second clock signal, wherein a first clear watchdog signal switches the watchdog timer unit from the first timer to the second timer.

3. The watchdog timer unit according to claim 2 , further comprising a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of the first or second timer.

4. The watchdog timer unit according to claim 1 , wherein the watchdog timer comprises a single timer clocked by the first clock signal and a first clear watchdog signal causes selection of the second clock signal to clock the single timer.

5. A watchdog timer unit configured to define a watchdog time period and generate a reset signal, wherein the watchdog timer unit comprises a timer receiving a clock signal through a clock input and a flip-flop being controlled by a clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of the timer or a logic 1, wherein after activation of the watchdog timer unit, the flip-flop is controlled to select the logic 1 until a first clear watchdog signal has been received whereupon the switch is controlled to select the output of the timer and wherein the watchdog timer unit is further configured to reset said timer upon receipt of further clear watchdog signals.

6. A watchdog timer unit configured to define a first and a second watchdog time period, wherein the watchdog timer unit comprises a clock input receiving a clock signal and is configured, after activation of the watchdog timer unit, to automatically select the first watchdog time period until a first clear watchdog signal has been received whereupon the watchdog timer unit switches to the second watchdog time period, wherein the first watchdog time period is set to be longer than the second watchdog time period, wherein the watchdog timer unit comprises a timer configured to be preset through a preset register in a first mode, wherein the preset register comprises bypass logic and wherein in a second mode the bypass logic is activated and the timer is preset directly bypassing the preset register, wherein upon activation of the watchdog timer unit operates in the second mode and the bypass logic is activated and upon receipt of a first clear watchdog signal, the watchdog timer unit operates in the first mode and the timer is preset through the preset register.

7. The watchdog timer unit according to claim 6 , wherein the timer is preset directly through a central processing unit.

8. The watchdog timer unit according to claim 6 , wherein the timer is preset directly through a start-up configuration register.

9. The microcontroller comprising a watchdog timer unit according to claim 6 , further comprising:
a central processing unit coupled with a plurality of peripheral devices through a system bus,
wherein the central processing unit is programmable to generate clear watchdog signals fed to the watchdog timer unit and wherein the watchdog timer unit is configured to generate a watchdog timeout signal for resetting the microcontroller.

10. The microcontroller according to claim 9 , wherein the timer is preset directly through the central processing unit.

11. The microcontroller according to claim 9 , wherein the timer is preset directly through a start-up configuration register of the microcontroller.

12. A microcontroller comprising a watchdog timer unit according to claim 1 , further comprising:
a central processing unit coupled with a plurality of peripheral devices through a system bus,
wherein the central processing unit is programmable to generate clear watchdog signals fed to the watchdog timer unit and wherein the watchdog timer unit is configured to generate a watchdog timeout signal for resetting the microcontroller.

13. The microcontroller according to claim 12 , wherein activation of the watchdog timer unit is performed automatically when the microcontroller is powered up thereby selecting the first watchdog time period and after receipt of the first clear watchdog signal generated by the central processing unit, the watchdog timer unit is configured to switch to the second timer.

14. The microcontroller according to claim 12 , further comprising an inverter coupled with an output of the second timer, wherein the watchdog timer unit further receives a power fail signal, wherein the logic is further configured to select between the first timer, the second timer and the output of the inverter, and wherein the watchdog timer unit selects the output of the inverter when a clear watchdog signal and a power fail signal is received.

15. The microcontroller according to claim 12 , wherein the first watchdog time period is defined by a first timer receiving the first clock signal and the second watchdog time period is defined by a second timer receiving the second clock signal, wherein a first clear watchdog signal switches the watchdog timer unit from the first timer to the second timer.

16. The microcontroller according to claim 15 , further comprising a clock generating unit configured to generate the first clock fed to the first timer and the second clock fed to the second timer.

17. The microcontroller according to claim 15 , further comprising a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of the first or second timer.

18. The microcontroller according to claim 12 , comprising a clock generating unit configured to generate the first clock signal and the second clock signal.

19. A microcontroller comprising:
a central processing unit coupled with a plurality of peripheral devices through a system bus; and
a watchdog timer unit receiving a clear watchdog signal and a clock signal and comprising a timer receiving said clock signal and a flip-flop being controlled by the clear watchdog signal and having an output controlling a switch that couples a reset output of the watchdog timer unit with either the output of the timer or a logic 1, wherein after activation of the watchdog timer unit, the flip-flop is controlled to select the logic 1 until a first clear watchdog signal has been received whereupon the switch is controlled to select the output of the timer and wherein the watchdog timer unit is further configured to reset said timer upon receipt of further clear watchdog signals.

20. A method for m

Assignees

• Microchip Tech Inc

Inventors

• Curtis Keith

Classifications

• G06F11/0721

  within a central processing unit [CPU] · CPC title

• G06F11/0757 Primary

  by exceeding a time limit, i.e. time-out, e.g. watchdogs · CPC title