Orientation indicator with pin signal alteration

Patent metadata

Field	Value
Publication number	US-10088514-B2
Application number	US-201514979243-A
Country	US
Kind code	B2
Filing date	Dec 22, 2015
Priority date	Jun 30, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

Techniques described herein include a method, system, and apparatus for detecting an orientation configuration. For example, an apparatus having an all-in-one port may include a first configuration pin and a second configuration pin. The apparatus may also include logic configured to enter into an accessory mode based on a presence of a first signal on the first configuration pin and a second signal on the second configuration pin. The logic may be further configured to provide an orientation indication by altering the first signal on the first configuration pin.

First claim

What is claimed is:

1. An apparatus having an all-in-one port, the all-in-one port, comprising:
a first configuration pin;
a second configuration pin;
logic configured to:
enter into a debug accessory mode based on a presence of a first signal on the first configuration pin and second signal on the second configuration pin;
provide an orientation indication by altering the first signal on the first configuration pin
generate a multiplexing configuration at a debug test system in response to the provided orientation indication.

2. The apparatus of claim 1 , wherein the orientation indication is provided before an operating system boots.

3. The apparatus of claim 1 , wherein the presence of the signal on both the first and second configuration pins is provided by the debug test system which is communicatively coupled to the all-in-one port.

4. The apparatus of claim 1 , wherein the debug test system provides a signal for a device under test to detect, the device under test to modify a multiplexing configuration.

5. The apparatus of claim 1 , wherein the logic is configured to alter the first signal on the first configuration pin by reducing a voltage level of the first signal on the first configuration pin.

6. The apparatus of claim 1 , wherein the logic is configured to alter the first signal on the first configuration pin by increasing a voltage level of the first signal on the first configuration pin.

7. The apparatus of claim 4 , wherein the apparatus is configured as:
a sink computing device during debug accessory mode; or
a source device during debug accessory mode.

8. The apparatus of claim 5 , wherein the logic is configured to reduce the voltage level on the first signal of the first configuration pin by grounding the first signal.

9. A method for orientation detection of an all-in-one port, comprising;
entering into a debug accessory mode based on a presence of a first signal on a first configuration pin and second signal on a second configuration pin of the all-in-one port;
providing an orientation indication by altering the first signal on the first configuration pin; and
generating a multiplexing configuration at a debug test system based on the provided orientation indication.

10. The method of claim 9 , wherein the orientation indication is provided without initializing an operating system software associated with the all-in-one port.

11. The method of claim 9 , wherein the presence of the signal on both the first and second configuration pins is provided by the debug test system.

12. The method of claim 9 , wherein altering the first signal on the first configuration pin comprises reducing a voltage level of the first signal on the first configuration pin.

13. The method of claim 9 , wherein altering the first signal on the first configuration pin comprises increasing a voltage level of the first signal on the first configuration pin.

14. The method of claim 9 , further comprising configuring the all-in-one port may be configured either as a source or a sink.

15. The method of claim 14 , wherein the all-in-one port is configured as:
a sink during debug accessory mode; or
a source during debug accessory mode.

16. The method of claim 12 , wherein reducing the voltage level on the first signal of the first configuration pin comprises grounding the first signal.

17. A system for orientation detection, comprising
a target comprising:
a first configuration pin;
a second configuration pin;
logic configured to:
enter into a debug accessory mode based on a presence of a first signal on the first configuration pin and second signal on the second configuration pin; and
provide an orientation indication by altering the first signal on the first configuration pin
generate a multiplexing configuration at a debug test system.

18. The system of claim 17 , wherein the orientation indication is provided without initializing an operating system software of the target.

19. The system of claim 17 , wherein the target may be either configured as a source or a sink, and wherein the target is configured as a sink computing device during debug accessory mode.

20. The system of claim 17 , wherein the target logic is configured to alter the first signal on the first configuration pin by reducing a voltage level of the first signal on the first configuration pin.

21. The system of claim 17 , wherein the target logic is configured to alter the first signal on the first configuration pin by increasing a voltage level of the first signal on the first configuration pin.

Assignees

• Intel Corp

Inventors

• Kuehnis Rolf
• Dunstan Robert A

Classifications

• G06F13/4068 Primary

  Electrical coupling · CPC title

• G01R31/68 Primary

  Testing of releasable connections, e.g. of terminals mounted on a printed circuit board · CPC title

• G06F13/40 Primary

  Bus structure {(for computer networks G06F15/163; for optical bus networks H04B10/25)} · CPC title

• G06F9/4411

  Configuring for operating with peripheral devices; Loading of device drivers · CPC title

• G01R31/043 Primary

  Physics · mapped topic