Ultrasonic gas flow meter based on FPGA and DSP

Patent metadata

Field	Value
Publication number	US-10088348-B2
Application number	US-201715688898-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Mar 24, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

An ultrasonic gas flow meter based on FPGA and DSP consists of ultrasonic gas transducers and sensor components, transmitting/receiving signal channel switch circuits, a driving signal generation and amplification circuit, an echo signal conditioning and collection circuit, a time sequential controlling and signal processing circuit, a man-machine interface, a serial communication module and a power management module, propagation time of ultrasonic echo waves is calculated by adopting a variable ratio threshold and zero-crossing detection method of tracking maximum peak of the echo signal to obtain gas flow rates.

First claim

What is claimed is:

1. An ultrasonic gas flow meter transmitter based on FPGA and DSP, wherein the ultrasonic gas flow meter transmitter consists of ultrasonic gas transducers and sensor components, transmitting/receiving signal channel switch circuits, a driving signal generation and amplification circuit, an echo signal conditioning and collection circuit, a time sequential controlling and signal processing circuit, a man-machine interface, a serial communication module and a power management module;
the ultrasonic gas transducers and sensor components are fixed on a gas pipeline;
the driving signal generation and amplification circuit consists of a high speed DAC signal generation and output circuit, a driving signal voltage and power amplification circuit;
the echo signal conditioning and collection circuit consists of a voltage amplification circuit, a bandpass filter circuit, an automatic gain control circuit, a single-ended-to-differential conversion circuit, a biasing circuit and a high speed ADC signal collection and conversion circuit;
the time sequential controlling and signal processing circuit consists of a FPGA circuit system and a DSP circuit system, the FPGA circuit system mainly consists of a FPGA chip, a FPGA chip serial configurator circuit, and a FPGA chip reset and configuration button circuit; the DSP circuit system mainly consists of a DSP chip and a DSP chip booting mode selection circuit.

2. The ultrasonic gas flow meter transmitter based on FPGA and DSP according to claim 1 , wherein the ultrasonic gas transducers and sensor components consist of four transducers, a pressure sensor and a temperature sensor, each of the transducers acts as a transmitting transducer as well as a receiving transducer.

3. The ultrasonic gas flow meter transmitter based on FPGA and DSP according to claim 2 , wherein the transmitting/receiving signal channel switch circuits consist of excitation strobe circuits, transformer amplification circuits and four echo strobe circuits; the four echo strobe circuits have the same structure, and connected with the transducers, respectively.

4. The ultrasonic gas flow meter transmitter based on FPGA and DSP according to claim 1 , wherein the FPGA chip is configured to temporarily store a conversion code value sent by the echo signal conditioning and collection circuit, the conversion code value will be transmitted to the DSP chip when delayed time is reached; the DSP chip is a master control chip, responsible for processing digital signals, human-computer Interaction and serial communication, and cooperated with the FPGA circuit system to control time sequence of the entire system; the DSP chip adopts digital filtering to eliminate noise in signals, a variable ratio threshold and zero-crossing detection method of tracking maximum peak of the echo signal is adopted to calculate a propagation time of an ultrasonic echo, so as to obtain gas flow rates.

5. The ultrasonic gas flow meter transmitter based on FPGA and DSP according to claim 3 , wherein the high speed DAC signal generation and output circuit consists of a dual differential line driver U- 2 , resistors R- 2 , R- 9 , R- 5 , R- 7 , R- 10 , R- 12 , R- 14 , R- 16 , R- 18 , R- 20 , R- 22 , R- 24 , R- 25 , capacitors C- 11 , C- 12 , C- 13 , C- 14 , C- 18 , C- 20 and C- 21 ; the high speed DAC signal generation and output circuit will output a high speed current signal to curb reflection and vibration;
the driving signal voltage and power amplification circuit consists of a low noise high speed operational amplifier U 1 , the dual differential line driver U 2 , resistors R 13 , R 14 , R 15 , R 16 , R 17 , R 22 , R 27 , R 28 , R 29 , R 30 , R 31 , R 32 , R 33 , R 35 , R 44 , capacitors C 25 and C 26 ;
the dual differential line driver U 2 outputs through two channels to reinforce ability of power amplification; driving signals after voltage and power amplification are finally transmitted to a next level.

6. The ultrasonic gas flow meter transmitter based on FPGA and DSP according to claim 3 , wherein the excitation strobe circuits comprise four bipolar operational amplifiers U 3 A, U 3 B, U 3 C and U 3 D; the transformer amplification circuits consist of transformers T 1 , T 2 , T 3 and T 4 , turn ratios of T 1 , T 2 , T 3 and T 4 are 1:10;
the four echo strobe circuits have the same structure; each of the echo strobe circuits consists of a dual low impedance single-pole single-throw switch U 4 , resistors R 47 , R 48 , R 49 and R 50 , an IC 1 terminal and an NIC 1 terminal of the dual low impedance single-pole single-throw switch U 4 are a strobe signal and a cut-off signal of a transducer output from DSP; when IC 1 is set to be high, S1 and D1 are gated, which access COM 1 to the succeeding echo signal conditioning and collection circuit; JUMP 1 is an adjusting terminal; the resistors R 48 , R 49 and R 50 are pull-down resistors; gated echo signals are output to succeeding circuits through the resistor R 47 .

7. The ultrasonic gas flow meter transmitter based on FPGA and DSP according to claim 3 , wherein in the echo signal conditioning and collection circuit,
the voltage amplification circuit consists of a low noise high speed operational amplifier U 10 , capacitors C 98 , C 100 , resistors R 59 , R 63 , R 64 , R 77 , R 81 , R 78 and R 83 , the resistors R 77 , R 81 and the low noise high speed operational amplifier U 10 form an anti-phase amplification circuit; the resistors R 78 , R 83 and the low noise high speed operational amplifier U 10 form an in-phase amplification circuit;
the bandpass filter circuit consists of a 4-order continuous time active power filter U 8 , resistors R 60 , R 62 , R 66 , R 67 , R 71 , R 72 , R 74 , R 75 , R 65 and R 57 , capacitor C 99 ; a center frequency, a bandwidth, a quality factor and a gain parameter of the filter are changed by adjusting a peripheral resistors R 60 , R 66 , R 71 , R 74 , R 62 , R 67 , R 72 and R 75 ; the resistor R 65 leads the echo signal after front-end conditioning to the filter, the resistor R 57 and the capacitor C 99 form a high pass filter;
the automatic gain control circuit consists of a high gain wide range adjustable gain amplifier U 9 , a low power consumption wide range operational amplifier U 12 , a low noise high speed operational amplifier U 7 , resistors R 55 , R 56 , R 76 , R 68 , R 79 , R 89 , R 90 , R 86 , R 85 , R 91 , R 88 and R 70 , capacitors C 101 and C 102 , a transistor Q 9 ; U 7 and its peripheral resistors R 55 , R 56 form an in-phase amplifier; the resistor R 76 is a pull-down resistor, the resistor R 68 is a Oohm connection resistor; automatic gain of the echo signal is achieved by U 9 , U 10 and a negative feedback structure established by peripheral discrete devices thereof;
the single-ended-to-differential conversion circuit consists of a low distortion differential ADC driver U 13 , resistors R 95 , R 96 , R 94 , R 93 , R 100 , R 98 , R 102 , R 104 , capacitors C 105 and C 111 , the resistors R 95 , R 96 , R 94 , R 93 and the capacitor C 105 are symmetrical to the resistors R 100 , R 98 , R 102 , R 104 and the capacitor C 111 , the resistor R 94 and capacitors C 105 , the resistor R 102 and capacitors C 111 form one-order low pass filtering respectively, V ocm is a common-mode input voltage;
the biasing circuit consists of an ordinary low noise operational amplifier U 15 , resistors R 99 and R 101 ;
the high speed ADC signal collection and conversion circuit consists of a high speed ADC chip U- 1 , resistors R- 1 , R- 27 , R- 28 , R- 29 , R- 35 , R- 37 , R- 48 , R- 154 , R- 155 , R- 156 , R- 157 , R- 158 , R- 159 , R- 160 , R- 161 , R- 3 , R- 4 , R- 6 , R- 8 , R- 11 , R- 13 , R- 15 , R- 17 , R- 19 , R- 21 , R- 23 , R- 26 , R- 30 , R- 31 , R- 32 , R- 33 , R- 34

Assignees

• Univ Hefei Technology

Inventors

• Xu Kejun
• Fang Min
• Wang Wei
• Zhu Wenjiao
• Shen Ziwen

Classifications

• G01F1/662

  Constructional details · CPC title

• G01F1/667 Primary

  Arrangements of transducers for ultrasonic flowmeters; Circuits for operating ultrasonic flowmeters · CPC title

• G01F1/74

  Devices for measuring flow of a fluid or flow of a fluent solid material in suspension in another fluid · CPC title

• G01N29/032

  by measuring attenuation of acoustic waves · CPC title

• G01N29/22

  Details {, e.g. general constructional or apparatus details} · CPC title