Growth of single crystal III-V semiconductors on amorphous substrates

Patent metadata

Field	Value
Publication number	US-10087547-B2
Application number	US-201615354063-A
Country	US
Kind code	B2
Filing date	Nov 17, 2016
Priority date	Dec 21, 2015
Publication date	Oct 2, 2018
Grant date	Oct 2, 2018

Abstract

This disclosure provides systems, methods, and apparatus related to the growth of single crystal III-V semiconductors on amorphous substrates. In one aspect, a shape of a semiconductor structure to be formed on an amorphous substrate is defined in a resist disposed on the amorphous substrate. A boron group element is deposited over the amorphous substrate. A ceramic material is deposited on the boron group element. The resist is removed from the amorphous substrate. The ceramic material is deposited to cover the boron group element. The amorphous substrate and materials deposited thereon are heated in the presence of a gas including a nitrogen group element to grow a single crystal semiconductor structure comprising the boron group element and the nitrogen group element.

First claim

What is claimed is:

1. A method comprising:
(a) defining a shape of a semiconductor structure to be formed on an amorphous substrate in a resist disposed on the amorphous substrate;
(b) depositing a boron group element over the amorphous substrate;
(c) depositing a ceramic material on the boron group element;
(d) removing the resist from the amorphous substrate;
(e) depositing the ceramic material to cover the boron group element; and
(f) heating the amorphous substrate and materials deposited thereon in the presence of a gas including a nitrogen group element to grow a single crystal semiconductor structure comprising the boron group element and the nitrogen group element.

2. The method of claim 1 , further comprising:
after operation (f), removing the ceramic material.

3. The method of claim 1 , further comprising:
after operation (a), depositing a nucleation layer on the amorphous substrate, and wherein the boron group element is deposited on the nucleation layer in operation (b).

4. The method of claim 3 , wherein the nucleation layer comprises an oxide material.

5. The method of claim 3 , wherein the nucleation layer is about 1 nanometers to 10 nanometers thick.

6. The method of claim 3 , wherein the nucleation layer comprises MoO x .

7. The method of claim 1 , wherein the boron group element is selected from a group consisting of boron, aluminum, gallium, and indium.

8. The method of claim 1 , wherein the boron group element deposited over the amorphous substrate has a thickness of about 10 nanometers to 5 microns thick.

9. The method of claim 1 , wherein the nitrogen group element is selected from a group consisting of nitrogen, phosphorus, arsenic, and antimony.

10. The method of claim 1 , wherein the amorphous substrate comprises a material selected from a group consisting of silicon dioxide, aluminum oxide, and an oxide glass.

11. The method of claim 1 , wherein the amorphous substrate and the materials deposited thereon are heated to about 300° C. to 1500° C.

12. The method of claim 1 , wherein the amorphous substrate and the materials deposited thereon are maintained at a temperature of about 300° C. to 1500° C. for about 5 minutes to 2 hours.

13. The method of claim 1 , wherein a length or a width of the single crystal semiconductor structure is about 10 nanometers to 500 microns.

14. The method of claim 1 , wherein a thickness of the ceramic material after operation (e) is about 10 nanometers to 200 nanometers.

15. The method of claim 1 , wherein operation (f) further includes heating the amorphous substrate and materials deposited thereon in the presence of a gas including a doping element.

16. The method of claim 1 , wherein the single crystal semiconductor structure comprises a semiconductor selected from a group consisting of boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum phosphide, aluminum arsenide, aluminum antimonide, gallium nitride, gallium phosphide, gallium arsenide, gallium antimonide, indium nitride, indium phosphide, indium arsenide, and indium antimonide.

17. The method of claim 1 , where in the resist comprises a photoresist or an electron resist.

18. The method of claim 1 , wherein the ceramic material comprises a material selected from a group consisting of silicon oxide (SiO x ), silicon nitride (SiN x ), and aluminum oxide (AlO x ).

19. The method of claim 1 , wherein after operation (e) the boron group element is in contact only with the ceramic material and the amorphous substrate.

20. A method comprising:
(a) defining a shape of a semiconductor structure to be formed in a resist deposited on an layer of SiO 2 ;
(b) depositing a layer of MoO x on the layer of SiO 2 ;
(c) depositing indium (In) on the layer of MoO x ;
(d) depositing SiO x on the In;
(e) removing the resist from the layer of SiO 2 ;
(f) depositing SiO x to cover the In; and
(g) heating the layer of SiO 2 and materials deposited thereon in the presence of PH 3 to grow a single crystal semiconductor structure comprising InP.

Assignees

• Chen Kevin
• Kapadia Rehan
• Javey Ali
• Univ California

Inventors

• Chen Kevin
• Kapadia Rehan
• Javey Ali

Classifications

• H10P14/3414

  being group IIIA-VIA materials · CPC title

• H10P14/3418

  Phosphides · CPC title

• H10P14/3251

  consisting of three or more layers · CPC title

• H10P14/3242

  Structure · CPC title

• H10P14/3238

  being insulating materials · CPC title