Method and device for reducing a computational load in high efficiency video coding

US10085028B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10085028-B2
Application numberUS-201514752043-A
CountryUS
Kind codeB2
Filing dateJun 26, 2015
Priority dateJun 26, 2014
Publication dateSep 25, 2018
Grant dateSep 25, 2018

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Abstract

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A method for reducing a computational load in high efficiency video coding includes generating a full rate distortion calculation list of selected intra coding modes where the intra coding modes including intra prediction modes and depth modeling modes. A rate distortion cost is determined, with a segment-wise depth coding mode being disabled, for each intra prediction mode in the full rate distortion calculation list and a smallest rate distortion cost intra prediction mode is selected. A rate distortion cost for a particular intra prediction mode is calculated with the segment-wise depth coding mode enabled. After comparison, one of the particular intra prediction mode and the smallest rate distortion cost intra prediction mode having the smallest rate distortion cost is applied to a prediction unit.

First claim

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What is claimed is: 1. A method for reducing a computational load in high efficiency video coding, comprising: generating a full rate distortion (RD) cost calculation list of selected intra coding modes, the intra coding modes including intra prediction modes and depth modeling modes; determining a RD cost for each intra prediction mode in the full RD cost calculation list wherein a segment-wise depth coding (SDC) mode for encoding image depth data is disabled for each intra prediction mode in the determination; selecting a smallest RD cost intra prediction mode having a smallest RD cost; calculating a RD cost for a particular intra prediction mode with the SDC mode enabled; comparing the RD cost of the particular intra prediction mode obtained for the SDC mode being enabled and the RD cost of the selected intra prediction mode having SDC mode disabled to determine which RD cost is smaller; and applying, to a prediction unit, one of the particular intra prediction mode having SDC mode enabled and the selected intra prediction mode having SDC mode disabled based on the smaller RD cost. 2. The method of claim 1 , further comprising: applying a checking condition to determine whether to calculate the RD cost for the particular intra prediction mode with the SDC mode enabled. 3. The method of claim 2 , wherein the checking condition comprises any one of: checking whether the selected intra prediction mode is a depth modeling mode; checking whether the selected intra prediction mode is a DC mode; checking whether the selected intra prediction mode is a Planar mode; checking whether the selected intra prediction mode is as same as any one of three modes occurring before other intra prediction modes in the full RD cost calculation list. 4. The method of claim 2 , wherein the checking condition comprises checking a block variance with a threshold value. 5. The method of claim 2 , wherein calculating the RD cost for a particular intra prediction mode with the SDC mode enabled is not performed for a certain checking condition. 6. The method of claim 1 , further comprising: selecting a second intra prediction mode having a second smallest RD cost and including the second intra prediction mode in the calculation and comparison steps; or selecting a second intra prediction mode having a third smallest RD cost and including the third intra prediction mode in the calculation and comparison steps; or selecting a second intra prediction mode from the full RD cost calculation list despite not having the smallest RD cost and including the second intra prediction mode in the calculation and comparison steps. 7. The method of claim 6 , wherein the second intra prediction mode is a first entry in the full RD cost calculation list, or the second intra prediction mode is a second entry in the full RD cost calculation list, or the second intra prediction mode is a third entry in the full RD cost calculation list. 8. The method of claim 1 , further comprising: determining whether to calculate the RD cost for the particular intra prediction mode in response to the selected intra prediction mode being a planar or DC intra prediction mode. 9. The method of claim 1 , further comprising: determining whether to calculate the RD cost for the particular intra prediction mode in response to a prediction unit variance being greater than a threshold value. 10. A device for reducing a computational load in high efficiency video coding, comprising: a memory configured to store data and instruction code; a processor, upon executing the instruction code, configured to: generate a full rate distortion (RD) cost calculation list of selected intra coding modes, the intra coding modes including intra prediction modes and depth modeling modes; determine a RD cost for each intra prediction mode in the full RD cost calculation list, wherein a segment-wise depth coding (SDC) mode for encoding image depth data is disabled for each intra prediction mode in the determination; select a smallest RD cost intra prediction mode having a smallest RD cost; calculate a RD cost for a particular intra prediction mode with the SDC mode enabled; compare the RD cost of the particular intra prediction mode obtained for SDC mode being enabled and the RD cost of the selected intra prediction mode having SDC mode disabled to determine which RD cost is smaller; and apply, to a prediction unit, one of the particular intra prediction mode having SDC mode enabled and the selected intra prediction mode having SDC mode disabled based on the smaller RD cost. 11. The device of claim 10 , wherein the processor is further configured to: apply a checking condition to determine whether to calculate the RD cost for the selected intra prediction mode with the SDC mode enabled. 12. The device of claim 11 , wherein the checking condition comprises any one of: checking whether the selected intra prediction mode is a depth modeling mode; checking whether the selected intra prediction mode is a DC mode; checking whether the selected intra prediction mode is a Planar mode; checking whether the selected intra prediction mode is as same as any one of three modes occurring before other intra prediction modes in the full RD cost calculation list. 13. The device of claim 11 , wherein the checking condition comprises checking a block variance with a threshold value. 14. The device of claim 11 , wherein calculating the RD cost for the particular intra prediction mode with the SDC mode enabled is not performed for a certain checking condition. 15. The device of claim 10 , wherein the processor is further configured to: select a second intra prediction mode having a second smallest RD cost and including the second intra prediction mode in the calculation and comparison steps; or select a second intra prediction mode having a third smallest RD cost and including the third intra prediction mode in the calculation and comparison steps; or select a second intra prediction mode from the full RD cost calculation list despite not having the smallest RD cost and including the second intra prediction mode in the calculation and comparison steps. 16. The device of claim 15 , wherein the second intra prediction mode is a first entry in the full RD cost calculation list, or the second intra prediction mode is a second entry in the full RD cost calculation list, or the second intra prediction mode is a third entry in the full RD cost calculation list. 17. The device of claim 10 , herein the processor is further configured to: determine whether to calculate the RD cost for the selected intra prediction mode in response to the selected intra prediction mode being a planar or DC intra prediction mode. 18. The device of claim 10 , wherein the processor is further configured to: determine whether to calculate the RD cost for the selected intra prediction mode in response to a prediction unit variance being greater than a threshold value. 19. A non-transitory computer readable medium including code for reducing a computational load in high efficiency video coding, the code upon being executed operable to: generate a full rate distortion (RD) cost calculation list of selected intra coding modes, the intra coding modes including intra prediction modes and depth modeling modes; determine a RD cost for each intra prediction mode in the full RD cost calculation list, wherein a segment-wise depth coding (SDC) mode for encoding image depth data is disabled for each intra prediction mode in the determination;

Assignees

Inventors

Classifications

  • H04N19/147Primary

    according to rate distortion criteria (rate-distortion as a criterion for motion estimation H04N19/567) · CPC title

  • H04N19/597Primary

    specially adapted for multi-view video sequence encoding · CPC title

  • Adaptive subdivision aspects, e.g. subdivision of a picture into rectangular or non-rectangular coding blocks · CPC title

  • the region being a block, e.g. a macroblock · CPC title

  • among a plurality of spatial predictive coding modes · CPC title

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What does patent US10085028B2 cover?
A method for reducing a computational load in high efficiency video coding includes generating a full rate distortion calculation list of selected intra coding modes where the intra coding modes including intra prediction modes and depth modeling modes. A rate distortion cost is determined, with a segment-wise depth coding mode being disabled, for each intra prediction mode in the full rate dis…
Who is the assignee on this patent?
Futurewei Technologies Inc, Univ Santa Clara
What technology area does this patent fall under?
Primary CPC classification H04N19/147. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).