Five-level inverter and application circuit of the same

Patent metadata

Field	Value
Publication number	US-10084392-B2
Application number	US-201615272857-A
Country	US
Kind code	B2
Filing date	Sep 22, 2016
Priority date	Oct 10, 2015
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A five-level inverter and its application circuit are provided. The five-level inverter is enabled to output multiple levels of voltage by controlling different conduction combinations of first, second, third, fourth, fifth, sixth, seventh, and eighth switch transistors, as well as a clamping capacitor. Two conduction combinations may be selected for outputting a positive voltage, with currents flowing through the clamping capacitor in opposite directions in the two conduction combinations. Therefore the voltage of the clamping capacitor can be balanced by controlling the two conduction combinations. Similarly, when outputting a negative voltage, the voltage of the clamping capacitor can be balanced by controlling other two conduction combinations. Therefore, a balance of power capacitor voltage can be achieved at full power and full modulation without adding an extra hardware circuit.

First claim

The invention claimed is:

1. A five-level inverter, connected between a positive terminal and a negative terminal of a direct-current power supply, and connected in parallel to a branch in which a first capacitor is connected in series to a second capacitor, wherein the five-level inverter comprises:
a first switch branch comprising a first unidirectional element and a first switch transistor, wherein a common terminal of the first unidirectional element and the first switch transistor is connected to a first terminal of the first capacitor;
a second switch branch comprising a second unidirectional element and a second switch transistor, wherein a common terminal of the second unidirectional element and the second switch transistor is connected to a first terminal of the first switch branch;
a third switch branch comprising a third unidirectional element and a third switch transistor, wherein a first terminal of the third switch branch is connected to a first terminal of the second switch branch, a second terminal of the first capacitor and a first terminal of the second capacitor;
a fourth switch branch comprising a fourth unidirectional element and a fourth switch transistor, wherein a first terminal of the fourth switch branch is connected to the first terminal of the third switch branch;
a fifth switch branch comprising a fifth unidirectional element and a fifth switch transistor, wherein a first terminal of the fifth switch branch is connected to the first terminal of the fourth switch branch;
a sixth switch branch comprising a sixth unidirectional element and a sixth switch transistor, wherein a first terminal of the sixth switch branch is connected to a common terminal of the fifth unidirectional element and the fifth switch transistor, a common terminal of the sixth unidirectional element and the sixth switch transistor is connected to a second terminal of the second capacitor;
a seventh switch transistor;
an eighth switch transistor; and
a clamping capacitor,
wherein a first terminal of the clamping capacitor is connected to a second terminal of the first switch branch, a second terminal of the second switch branch, a second terminal of the third switch branch and a first terminal of the seventh switch transistor;
wherein a second terminal of the clamping capacitor is connected to a second terminal of the fourth switch branch, a second terminal of the fifth switch branch, a second terminal of the sixth switch branch and a second terminal of the eighth switch transistor;
wherein a first terminal of the eighth switch transistor is connected to a second terminal of the seventh switch transistor at a connection point connected to an output terminal of the five-level inverter; and
wherein each of the seventh switch transistor and the eighth switch transistor is a switch transistor providing a bidirectional power path.

2. The five-level inverter according to claim 1 , wherein:
an input terminal of the second unidirectional element is the first terminal of the second switch branch;
a second terminal of the second switch transistor is the second terminal of the second switch branch;
a first terminal of the second switch transistor is connected to an output terminal of the second unidirectional element at a connection point connected to the first terminal of the first switch branch;
a second terminal of the third switch transistor is the first terminal of the third switch branch;
a first terminal of the third switch transistor is connected to an output terminal of the third unidirectional element;
an input terminal of the third unidirectional element is the second terminal of the third switch branch;
an input terminal of the fourth unidirectional element is the first terminal of the fourth switch branch;
an output terminal of the fourth unidirectional element is connected to a first terminal of the fourth switch transistor;
a second terminal of the fourth switch transistor is the second terminal of the fourth switch branch;
an input terminal of the fifth unidirectional element is connected to a second terminal of the fifth switch transistor at a connection point connected to the first terminal of the sixth switch branch;
an output terminal of the fifth unidirectional element is the first terminal of the fifth switch branch; and
a first terminal of the fifth switch transistor is the second terminal of the fifth switch branch.

3. The five-level inverter according to claim 2 , wherein:
an output terminal of the first unidirectional element is connected to a first terminal of the first switch transistor at a connection point connected to the first terminal of the first capacitor;
an input terminal of the first unidirectional element is the first terminal of the first switch branch;
a second terminal of the first switch transistor is the second terminal of the first switch branch;
an input terminal of the sixth unidirectional element is connected to a second terminal of the sixth switch transistor at a connection point connected to the second terminal of the second capacitor;
an output terminal of the sixth unidirectional element is the first terminal of the sixth switch branch;
a first terminal of the sixth switch transistor is the second terminal of the sixth switch branch; and
each of the second switch transistor, the third switch transistor, the fourth switch transistor and the fifth switch transistor comprises a body diode or is connected in reverse-parallel to a diode.

4. The five-level inverter according to claim 3 , wherein the five-level inverter operates in one of the following eight working modes:
a first mode, in which the first switch transistor and the seventh switch transistor are in an on state, and the other switch transistors are in an off state;
a second mode, in which the first switch transistor and the eighth switch transistor are in an on state, and the other switch transistors are in an off state;
a third mode, in which the fourth switch transistor, the fifth switch transistor and the seventh switch transistor are in an on state, and the other switch transistors are in an off state;
a fourth mode, in which the fourth switch transistor, the fifth switch transistor and the eighth switch transistor are in an on state, and the other switch transistors are in an off state;
a fifth mode, in which the second switch transistor, the third switch transistor and the seventh switch transistor are in an on state, and the other switch transistors are in an off state;
a sixth mode, in which the second switch transistor, the third switch transistor and the eighth switch transistor are in an on state, and the other switch transistors are in an off state;
a seventh mode, in which the sixth switch transistor and the seventh switch transistor are in an on state, and the other switch transistors are in an off state; and
an eighth mode, in which the sixth switch transistor and the eighth switch transistor are in an on state, and the other switch transistors are in an off state.

5. The five-level inverter according to claim 3 , wherein:
the five-level inverter further comprises:
a ninth switch transistor connected in reverse-parallel to the first unidirectional element; and
a tenth switch transistor connected in reverse-parallel to the sixth unidirectional element; or

the five-level inverter further comprises:
an eleventh switch transistor connected in reverse-parallel to the second unidirectional element; and
a twelfth switch transistor connected in reverse-parallel to the fifth unidirectional element; or

the five-level inverter further comprises:
a thirteenth switch transistor connected in reverse-parallel to the third unidirectional element; and
a fourteenth switch transistor connected in reverse-parallel to the fourth unidirectional element.

Assignees

• Sungrow Power Supply Co Ltd

Inventors

• Shen Tan
• Wang Peng
• Geng Houlai
• Hu Bing
• Bie Wei
• Dai Shangfang

Classifications

• H02M7/537 Primary

  using semiconductor devices only, e.g. single switched pulse inverters · CPC title

• H02M1/44

  Circuits or arrangements for compensating for electromagnetic interference in converters or inverters · CPC title

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• H02M7/487 Primary

  Neutral point clamped inverters · CPC title

• H02M7/4837

  Flying capacitor converters · CPC title