Charge pump suitable for low input voltages

Patent metadata

Field	Value
Publication number	US-10084375-B2
Application number	US-201615360041-A
Country	US
Kind code	B2
Filing date	Nov 23, 2016
Priority date	Nov 25, 2015
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A charge pump circuit suitable for low input voltages is presented. The charge pump circuit has a first clock signal generator, a second clock signal generator, and n voltage doubler circuits. The voltage doubler has an input, an output, a first capacitor connected to the first clock signal generator, a second capacitor connected to the second clock signal generator, a first NMOST having the source connected to the input and the drain connected to the first capacitor, a second NMOST having the connected to the source of the first NMOST and the drain connected to second capacitor, a first PMOST having the drain connected to the first capacitor and the source connected to the output, a second PMOST having the source connected to the source of the first PMOST and the drain connected to the second capacitor.

First claim

What is claimed is:

1. A charge pump circuit comprising:
a number n of voltage doubler circuits, with n>1;
a first clock signal generator configured to generate a first clock signal;
a second clock signal generator configured to generate a second clock signal, wherein the second clock signal is low when the first clock signal is high and the second clock signal is high when the first clock signal is low;
wherein each one of the n voltage doubler circuits comprises:
an input;
an output;
a first capacitor having a first and a second terminal, wherein the first terminal is connected to the first clock signal generator;
a second capacitor having a first and a second terminal, wherein the first terminal is connected to the second clock signal generator;
a first N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the first NMOST is connected to the input of the voltage doubler circuit and the drain of the first NMOST is connected to the second terminal of the first capacitor;
a second N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the second NMOST is connected to the source of the first NMOST and the drain of the second NMOST is connected to the second terminal of the second capacitor;
a first P-type metal oxide semiconductor transistor (PMOST) having a source, a drain and a gate, wherein the drain of the first PMOST is connected to the second terminal of the first capacitor and the source of the first PMOST is connected to the output of the voltage doubler circuit;
a second P-type metal oxide semiconductor transistor (PMOST) having a source, a drain and a gate, wherein the source of the second PMOST is connected to the source of the first PMOST and the drain of the second PMOST is connected to the second terminal of the second capacitor;
wherein the output of the i-th voltage doubler circuit is the input of the (i+1)-th voltage doubler circuit for every i from 1 to n−1;
wherein at least a k-th voltage doubler circuit of the n voltage doubler circuits has:
the gate of the first PMOST connected to the second terminal of the second capacitor of an l-th voltage doubler circuit and/or the gate of the second PMOST connected to the second terminal of the first capacitor of an m-th voltage doubler circuit, wherein l<k and m<k;
and/or the gate of the first NMOST connected to the second terminal of the second capacitor of a d-th voltage doubler circuit and/or the gate of the second NMOST connected to the second terminal of the first capacitor of a j-th voltage doubler circuit, wherein d>k and j>k.

2. The charge pump circuit of claim 1 , further comprising
an (n+1)-th stage, wherein the (n+1)-th stage comprises:
a first capacitor having a first and a second terminal, wherein the first terminal of the first capacitor is connected to the first clock signal generator;
a second capacitor having a first and a second terminal, wherein the first terminal of the second capacitor is connected to the second clock signal generator;
a first N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the first NMOST is connected to the output of the n-th voltage doubler, the drain of the first NMOST is connected to the second terminal of the first capacitor and the gate of the first NMOST is connected to the second terminal of the second capacitor;
a second N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the second NMOST is connected to the output of the n-th voltage doubler, the drain of the second NMOST is connected to the second terminal of the second capacitor, and the gate of the second NMOST is connected to the second terminal of the first capacitor.

3. A voltage doubler circuit comprising:
an input;
an output;
a first capacitor having a first and a second terminal, wherein the first terminal is configured to receive a first clock signal;
a second capacitor having a first and a second terminal, wherein the first terminal is configured to receive a second clock signal and wherein the second clock signal is low when the first clock signal is high and the second clock signal is high when the first clock signal is low;
a first N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the first NMOST is connected the input of the voltage doubler circuit and the drain of the first NMOST is connected to the second terminal of the first capacitor;
a second N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the second NMOST is connected to the source of the first NMOST and the drain of the second NMOST is connected to the second terminal of the second capacitor;
a first P-type metal oxide semiconductor transistor (PMOST) having a source, a drain and a gate, wherein the drain of the first PMOST is connected to the second terminal of the first capacitor and the source of the first PMOST is connected to the output of the voltage doubler circuit; and
a second P-type metal oxide semiconductor (PMOST) having a source, a drain and a gate, wherein the source of the second PMOST is connected to the source of the first PMOST and the drain of the second PMOST is connected to the second terminal of the second capacitor;

wherein the voltage doubler circuit further comprises:
a third capacitor having a first terminal configured to receive the first clock signal and a second terminal connected to the gate of the second NMOST,
a fourth capacitor having a first terminal configured to receive the second clock signal and a second terminal connected to the gate of the first NMOST,
a third P-type metal oxide semiconductor transistor (PMOST) having a source, a drain and a gate, wherein the source of the third PMOST is connected to the second terminal of the first capacitor, the drain of the third PMOST is connected to the second terminal of the fourth capacitor, and the gate of the third PMOST is connected to the second terminal of the second capacitor, and
a fourth P-type metal oxide semiconductor transistor (PMOST) having a source, a drain and a gate, wherein the source of the fourth PMOST is connected to the second terminal of the second capacitor, the drain of the fourth PMOST is connected to the second terminal of the third capacitor, and the gate of the fourth PMOST is connected to the second terminal of the first capacitor; and/or
fifth capacitor having a first terminal configured to receive the first clock signal and a second terminal connected to the gate of the second PMOST, a sixth capacitor having a first terminal configured to receive the second clock signal and a second terminal connected to the gate of the first PMOST, a third N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the third NMOST is connected to the second terminal of the first capacitor, the drain of the third NMOST is connected to the second terminal of the sixth capacitor, and the gate of the third NMOST is connected to the second terminal of the second capacitor, a fourth N-type metal oxide semiconductor transistor (NMOST) having a source, a drain and a gate, wherein the source of the fourth NMOST is connected to the second terminal of the second capacitor, the drain of the fourth NMOST is connected to the second terminal of the fifth capacitor, and the gate of the fourth NMOST is connected to the second terminal of the first capacitor.

4. The charge pump circuit according to claim 1 , or the voltage doubler circuit according to claim 3 , wherein at least the k-th voltage doubler circuit of the n voltage doubler circuits of the charge pump circuit according to cl

Assignees

• Dialog Semiconductor Bv

Inventors

• Kruiskamp Marinus Wilhelmus

Classifications

• H02M3/073 Primary

  Charge pumps of the Schenkel-type · CPC title

• H02M2003/077

  Electricity · mapped topic

• H02M3/077

  with parallel connected charge pump stages · CPC title