Methods of making multichannel devices with improved performance

Patent metadata

Field	Value
Publication number	US-10084075-B2
Application number	US-201715624445-A
Country	US
Kind code	B2
Filing date	Jun 15, 2017
Priority date	Nov 5, 2014
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth.

First claim

What is claimed is:

1. A method of forming a transistor device, the method comprising:
forming a superlattice structure comprising a plurality of heterostructures over a base structure by sequentially depositing each layer of the plurality of heterostructures over the base structure with one layer of each heterostructure being doped;
etching away openings in the superlattice structure over a channel region to form a castellated region in the channel region of alternating multichannel ridges with edges and nonchannel openings;
performing a gate contact fill process to form a gate contact that wraps around and substantially surrounds the top and sides of each of the alternating multichannel ridges along at least a portion of its depth and connects each one of the alternating multichannel ridges to one another through the non-channel openings; and
varying at least one parameter of at least one of corresponding parallel heterostructures of each of the alternating multichannel ridges, the at least one parameter being a dopant concentration for each heterostructure, such that longer width channels associated with a given heterostructure are doped with less dopant concentration than shorter width channels associated with a given heterostructure for each of the plurality of heterostructures to substantially equalize the pinch-off voltage of each channel of the SLCFET during operation.

2. The method of claim 1 , wherein the at least one parameter further comprises a thickness.

3. The method of claim 1 , wherein the at least one parameter further comprises a thickness, such that each inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure for each of the alternating multichannel ridges.

4. The method of claim 1 , wherein the at least one parameter further comprises a thickness, such that every other inner heterostructure is formed with a greater thickness than a thickness of at least one of a top heterostructure and a bottom heterostructure for each of the alternating multichannel ridges.

Assignees

• Nechay Bettina A
• Gupta Shalini
• King Matthew Russell
• Stewart Eric J
• Howell Robert S
• Parke Justin Andrew
• Cramer Harlan Carl
• Henry Howell George
• Freitag Ronald G
• Renaldo Karen Marie
• Northrop Grumman Systems Corp

Inventors

• Nechay Bettina A
• Gupta Shalini
• King Matthew Russell
• Stewart Eric J
• Howell Robert S
• Parke Justin Andrew
• Cramer Harlan Carl
• Henry Howell George
• Freitag Ronald G
• Renaldo Karen Marie

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H01L21/3065

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic

• H01L29/7785 Primary

  Electricity · mapped topic

• H01L29/2003

  Electricity · mapped topic