System, method and computer-accessible medium for security verification of third party intellectual property cores

Patent metadata

Field	Value
Publication number	US-10083303-B2
Application number	US-201514958585-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Oct 3, 2014
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

An exemplary system, method and computer-accessible medium for detecting the presence of a Trojan(s) in a circuit(s), can include, for example, receiving information related to a property(s) configured to determine the presence of the Trojan(s), and determining the presence of the Trojan(s) based on the property(s) and a design(s) of the circuit(s) using a bounded model checking tool.

First claim

What is claimed is:

1. A non-transitory computer-accessible medium having stored thereon computer-executable instructions for determining a presence of at least one Trojan in at least one design of at least one intellectual property (IP) core, wherein, when a computer arrangement executes the instructions, the computer arrangement is configured to perform procedures comprising:
receiving electronic data related to (i) at least one property and (ii) a hardware description of the at least one design;
deriving a satisfiability solving engine based on the at least one property and the hardware description using a bounded model checking (BMC) engine;
generating at least two copies of the at least one design;
forcing logic contained in each of the at least two copies to at least one particular value; and
determining the presence of the at least one Trojan by applying the satisfiability solving engine to the at least two copies of the at least one design.

2. The computer-accessible medium of claim 1 , wherein the at least one design includes a software description of the at least one design.

3. The computer-accessible medium of claim 1 , wherein the determining of the presence of the at least one Trojan includes generating at least one Boolean formula using the BMC engine.

4. The computer-accessible medium of claim 3 , wherein the computer arrangement is further configured to assign further particular values to the at least one Boolean formula using a satisfiability solving engine.

5. The computer-accessible medium of claim 4 , wherein the computer arrangement is further configured to generate an indication of the presence of the at least one Trojan if the at least one Boolean formula evaluates to 1 using the particular values.

6. The computer-accessible medium of claim 1 , further comprising at least one bound.

7. The computer-accessible medium of claim 6 , wherein the determining of the presence of the at least one Trojan is further based on the at least one bound.

8. The computer-accessible medium of claim 6 , wherein the at least one bound is a particular number of clock cycles.

9. The computer-accessible medium of claim 1 , wherein the at least one property includes a detection that the at least one Trojan leaks at least one secret.

10. The computer-accessible medium of claim 9 , wherein the at least one secret includes at least one of (i) at least one cryptographic key, (ii) at least one plaintext secret, or (iii) at least one intermediate computation.

11. The computer-accessible medium of claim 1 , wherein the at least one property includes a detection that the at least one Trojan leaks at least one subset of at least one secret.

12. The computer-accessible medium of claim 1 , wherein the at least one property includes a detection that the at least one Trojan is triggered over a plurality of clock cycles.

13. The computer-accessible medium of claim 1 , wherein the at least one property includes a detection of at least one of at least one direct polarity and at least one indirect polarity.

14. The computer-accessible medium of claim 1 , wherein the at least one design includes at least one circuit.

15. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to determine assignments to an input of the at least one design over a plurality of clock cycles using the at least one property.

16. The computer-accessible medium of claim 15 , wherein the determining of the presence of the at least one Trojan utilizes a set of inputs over the clock cycles that violate the at least one property.

17. The computer-accessible medium of claim 1 , wherein the at least one property includes a strict avalanche criterion property.

18. The computer-accessible medium of claim 17 , wherein the computer arrangement is further configured to determine the strict avalanche criterion property.

19. The computer-accessible medium of claim 18 , wherein the computer arrangement determines the strict avalanche criterion property using at least two seeds for a pseudo random number generator.

20. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to generate a plurality of states that satisfy the at least one property using the BMC engine.

21. The computer-accessible medium of claim 20 , wherein the computer arrangement determines the presence of the at least one Trojan based on the states.

22. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to generate at least one witness that violates the at least one property using the BMC engine.

23. The computer-accessible medium of claim 22 , wherein the computer arrangement determines the presence of the at least one Trojan based on the at least one witness.

24. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to generate at least one temporal logic design of the at least one design using the BMC checking engine.

25. The computer-accessible medium of claim 24 , wherein the computer arrangement is further configured to determine the presence of the at least one Trojan based on the at least one temporal logic design.

26. The computer-accessible medium of claim 1 , wherein the computer arrangement is further configured to (i) force the logic contained in a first copy of the at least two copies to a logic 0, and (ii) force the logic contained in a second copy of the at least two copies to a logic 1.

27. A method for determining a presence of at least one Trojan in at least one design of at least one intellectual property (IP) core, comprising:
receiving electronic data related to (i) at least one property and (ii) a hardware description of the at least one design;
deriving a satisfiability solving engine based on the at least one property and the hardware description using a bounded model checking (BMC) engine;
generating at least two copies of the at least one design;
forcing logic contained in each of the at least two copies to at least one particular value; and
determining the presence of the at least one Trojan by applying the satisfiability solving engine to the at least two copies of the at least one design.

28. A system for determining a presence of at least one Trojan in at least one design of at least one intellectual property (IP) core, comprising:
a computer hardware arrangement configured to:
receive electronic data related to (i) at least one property and (ii) a hardware description of the at least one design;
derive a satisfiability solving engine based on the at least one property and the hardware description using a bounded model checking (BMC) engine;
generate at least two copies of the at least one design;
force logic contained in each of the at least two copies to at least one particular value; and
determine the presence of the at least one Trojan by applying the satisfiability solving engine to the at least two copies of the at least one design.

29. The method of claim 27 , wherein (i) the logic contained in a first copy of the at two copies is forced to a logic 0, and (ii) the logic contained in a second copy of the at least two copies is forced to a logic 1.

30. The system of claim 28 , wherein the computer hardware arrangement is configured to (i) force the logic contained in a first copy of

Assignees

• Univ New York

Inventors

• Vedula Vivekananda
• Rajendran Jeyavijayan
• Dhandayuthapany Arunshankar
• Karri Ramesh

Classifications

• G06F21/577 Primary

  Assessing vulnerabilities and evaluating computer system security · CPC title

• G06F21/76

  in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title

• G06F21/56

  Computer malware detection or handling, e.g. anti-virus arrangements · CPC title