Using direct sums and invariance groups to test partially symmetric quantum-logic circuits

Patent metadata

Field	Value
Publication number	US-10082539-B2
Application number	US-201615194645-A
Country	US
Kind code	B2
Filing date	Jun 28, 2016
Priority date	Jun 28, 2016
Publication date	Sep 25, 2018
Grant date	Sep 25, 2018

Abstract

A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.

First claim

What is claimed is:

1. A quantum-logic test-development system comprising a processor, a memory coupled to the processor, and a computer-readable hardware storage device coupled to the processor, the storage device containing program code configured to be run by the processor via the memory to implement a method for using direct sums and invariance groups to test partially symmetric quantum-logic circuits, the method comprising: the system receiving architectural information about a quantum-logic circuit that has at least four inputs and at least one output; the system, as a function of the architectural information, dividing the at least four inputs into two or more non-intersecting subsets; the system creating a set of groups that each comprise a subset, selected from the set of two or more non-intersecting subsets, and one or more permutation operations, where no individual operation of the one or more permutation operations comprises any characteristic capable of precluding the individual operation from-being performed upon inputs comprised by the selected subset; the system generating a direct sum of the set of groups, where the direct sum identifies an invariance group of a function that represents functionality of the quantum-logic circuit, where the invariance group comprises a set of invariant permutations, where each permutation of the set of invariant permutations identifies a permutation of two or more inputs comprised by one and only one subset of the two or more non-intersecting subsets, and where no output of the quantum-logic circuit changes state when any permutation of the set of invariant permutations is performed upon the at least four inputs of the quantum-logic circuit; the system optimizing a procedure for testing the quantum-logic circuit, where the procedure comprises a series of tests that each verify correct operation of the quantum-logic circuit in response to receiving a distinct input vector of a set of input vectors, and where the optimizing comprises deleting from the series of tests any test associated with an input vector, where the input vector comprises no characteristic capable of precluding the input vector from being generated by performing a permutation of the set of invariant permutations upon a distinct input vector associated with a previous test of the series of tests.

2. The system of claim 1 , where the received architectural information identifies a number of inputs of the circuit, a number of outputs of the circuit, a maximum number of concurrent states associated with each input of the circuit, and a maximum number of concurrent states associated with each output of the circuit.

3. The system of claim 2 , where a first group of the set of groups comprises a first subset of the non-intersecting subsets and a first set of all permutations capable of being performed upon inputs that consist solely of inputs comprised by the first subset.

4. The system of claim 2 , where a direct sum of a first group of the set of groups, consisting of a first subset of the non-intersecting subsets and a first set of all permutations capable of being performed upon the first subset, and a second group of the set of groups, consisting of a second subset of the non-intersecting subsets and a second set of all permutations capable of being performed upon the second subset, generates an invariance group that comprises: i) a Cartesian product of the first set of permutations and the second set of permutations, and ii) a set formed by a union of the first subset and the second subset.

5. The system of claim 2 , where f k ( x ) is a semi-recursive function that returns an output state produced by the quantum-logic module in response to receiving an input vector x .

6. The system of claim 5 , where f k ( x ) represented by the equation:

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Assignees

• IBM

Inventors

• Jasionowski Pawel

Classifications

• H03K19/0002

  Multistate logic (H03K19/02 takes precedence) · CPC title

• G01R31/31937

  Timing aspects, e.g. measuring propagation delay (G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24) · CPC title

• H03K19/017509

  Interface arrangements · CPC title

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F17/16

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title