Clock synchronization method, device, and system
US-2024421929-A1 · Dec 19, 2024 · US
US10080207B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10080207-B2 |
| Application number | US-201715686556-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 25, 2017 |
| Priority date | Jun 16, 2015 |
| Publication date | Sep 18, 2018 |
| Grant date | Sep 18, 2018 |
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An audio device includes a signal input interface, a first output interface, a second output interface, at least one processing circuit configured as a buffer control portion, at least one memory configured to store an audio signal. The buffer control portion sets a second reading position at a position that precedes a first reading position of the first output interface by delay time, and, when starting output of the audio signal, writes silent data for the delay time in the memory and sets the first reading position at the head of the silent data.
Opening claim text (preview).
What is claimed is: 1. An audio device comprising: a signal input interface configured to input an audio signal; a first output interface; a second output interface; at least one processing circuit configured as a buffer control portion; and at least one memory configured to store the audio signal and instruction that, when executed by the at least one processing circuit, wherein: the buffer control portion sets a first reading position being a reading position of the audio signal stored in the memory with respect to the first output interface, a second reading position being a reading position of the audio signal stored in the memory with respect to the second output interface, and a minimum buffer position being a most preceding position of the audio signal in the memory; and in a case in which, in a middle of reading the audio signal from the memory to the first output interface, the audio signal is newly read from the memory to the second output interface, when a buffer amount of the memory is equal to or more than delay time, the buffer control portion sets the second reading position at a position that precedes the first reading position by the delay time, and, when the buffer amount of the memory is less than the delay time, the buffer control portion sets the second reading position at the minimum buffer position, moves the first reading position to a position that goes back from the minimum buffer position by the delay time, and writes silent data for time of movement from the first reading position before the movement to the first reading position after the movement. 2. The audio device according to claim 1 , wherein the memory includes: a first memory; and a second memory; the at least one processing circuit is further configured to: write the audio signal in the first memory and the second memory; and read the audio signal from the memory; the first reading position is set in the first memory; and the second reading position is set in the second memory. 3. The audio device according to claim 2 , wherein the at least one processing circuit is further configured to discard the audio signal before the second reading position in the second memory. 4. An audio system comprising: the audio device according to claim 1 ; a first reproducing device configured to reproduce the audio signal that is output from the first output interface; and a second reproducing device configured to reproduce the audio signal that is output from the second output interface, wherein the delay time corresponds to a time lag between input of the audio signal to the first reproducing device and input of the audio signal to the second reproducing device. 5. The audio system according to claim 4 , wherein a transmission system from the first output interface to the first reproducing device and a transmission system from the second output interface to the second reproducing device have different transmission rates.
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