Wideband amplifier circuits and methods

Patent metadata

Field	Value
Publication number	US-10079582-B2
Application number	US-201615242404-A
Country	US
Kind code	B2
Filing date	Aug 19, 2016
Priority date	Dec 18, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

An wideband amplifier circuit such as a transimpedance amplifier achieves improved amplifier and/or system performance, such as a reduced input impedance. The transimpedance amplifier may use a complementary common gate stage that receives an input signal and generates current to a current summing stage. In one instance, an input current is received by a complimentary common gate stage that includes a first common gate transistor and a second common gate transistor, each having different polarities, in which the first terminals of each of the transistors are configured to receive the input current. Each of the transistors generates an output current to a current summing stage that generates an output voltage at an output terminal. The output voltage may be based on the combined currents from the first common gate transistor and second common gate transistor.

First claim

What is claimed is:

1. A circuit comprising:
a first common gate transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is configured to receive an input signal, and the first common gate transistor having a first polarity;
a second common gate transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second common gate transistor is coupled to the first terminal of the first common gate transistor and configured to receive the input signal, the second common gate transistor having a second polarity; and
a first current summing stage having a current summing transistor, a gate of the current summing transistor configured to receive an external bias voltage, a first terminal of the first current summing stage coupled to the second terminal of the first common gate transistor, a second terminal coupled to the second terminal of the second common gate transistor, and a first output terminal configured to generate a first output voltage based at least in part on combined currents from the first common gate transistor and the second common gate transistor.

2. The circuit of claim 1 further comprising a first common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first common source transistor is configured to receive an inverse of the input signal and the second terminal is coupled to a second terminal of one of the first common gate transistor or the second common gate transistor.

3. The circuit of claim 2 wherein the first common source transistor is configured to conduct a bias current, wherein the second terminal of the first common gate transistor receives a first portion of the bias current and the first terminal of the first current summing stage receives the second portion of the bias current, and wherein the first portion of the bias current is greater than the second portion of the bias current.

4. The circuit of claim 2 wherein the first common gate transistor is at least two times greater in size than a first transistor in the first current summing stage.

5. The circuit of claim 1 , the first current summing stage comprising:
a first cascode transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first cascode transistor is coupled to the second terminal of the first common gate transistor; and
a second cascode transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second cascode transistor is coupled to the second terminal of the second common gate transistor.

6. The circuit of claim 1 , wherein the input signal is a first component of a differential signal, the circuit further comprising:
a third common gate transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal is configured to receive a second component of the differential signal, the third common gate transistor having the first polarity; and
a fourth common gate transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fourth common gate transistor is coupled to the first terminal of the third common gate transistor and configured to receive the second component of the differential signal, the fourth common gate transistor having the second polarity,
wherein the first output voltage of the first current summing stage is the first component of a differential output signal, wherein the first current summing stage further comprises a third terminal coupled to the second terminal of the third common gate transistor, a fourth terminal coupled to the second terminal of the fourth common gate transistor, and a second output terminal configured to generate a second output voltage based at least in part on combined currents from the third common gate transistor and the fourth common gate transistor, wherein the second output voltage is the second component of the differential output signal.

7. The circuit of claim 6 , further comprising:
a first common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the first common source transistor is configured to receive the second component of the differential signal, and the second terminal is coupled to the second terminal of one of the first common gate transistor or the second common gate transistor; and
a second common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the second common source transistor is configured to receive the first component of the differential signal and the second terminal is coupled to the second terminal of one of the third common gate transistor or the fourth common gate transistor.

8. The circuit of claim 7 , wherein the second terminal of the first common source transistor is coupled to the second terminal of the first common gate transistor and the second terminal of the second common source transistor is coupled to the second terminal of the third common gate transistor.

9. The circuit of claim 8 , further comprising:
a third common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the third common source transistor is configured to receive the second component of the differential signal, and the second terminal is coupled to the second terminal of the second common gate transistor; and
a fourth common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the fourth common source transistor is configured to receive the first component of the differential signal and the second terminal is coupled to the second terminal of the fourth common gate transistor.

10. The circuit of claim 7 , wherein the second terminal of the first common source transistor is coupled to the second terminal of the second common gate transistor and the second terminal of the second common source transistor is coupled to the second terminal of the fourth common gate transistor.

11. The circuit of claim 7 , further comprising:
a third common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the third common source transistor is configured to receive the second component of the differential signal and the second terminal is coupled to the second terminal of the first common source transistor; and
a fourth common source transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the fourth common source transistor is configured to receive the first component of the differential signal and the second terminal is coupled to the second terminal of the third common source transistor.

12. The circuit of claim 11 , wherein, in a first mode, the first common gate transistor, the second common gate transistor, the third common gate transistor, and the fourth common gate transistor are configured to be off and the third common source transistor and the fourth common source transistor are configured to be on, and in a second mode, the first common gate transistor, the second common gate transistor, the third common gate transistor, and the fourth common gate transistor are configured to be on and the third common source transistor and the fourth common source transistor are configured to be off.

13. The circuit of claim 7 , further comprising:
a first plurality of switches coupled to the

Assignees

• Qualcomm Inc

Inventors

• Gathman Timothy

Classifications

• H03F2203/45288

  Differential amplifier with circuit arrangements to enhance the transconductance · CPC title

• H03F1/086 Primary

  with FET's · CPC title

• H03F3/72

  Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal · CPC title

• H03F2203/45526

  the FBC comprising a resistor-capacitor combination and being coupled between the LC and the IC · CPC title

• H03F2203/45091

  Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type · CPC title