Low distortion multiple power amplifier power supply

Patent metadata

Field	Value
Publication number	US-10079575-B2
Application number	US-201615382773-A
Country	US
Kind code	B2
Filing date	Dec 19, 2016
Priority date	Dec 17, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A PA power supply, which includes a first ET power supply, power supply control circuitry, a first PMOS switching element, and a second PMOS switching element, is disclosed. During a first operating mode, the power supply control circuitry selects an OFF state of the first PMOS switching element, selects an ON state of the second PMOS switching element, and adjusts a voltage of a first switch control signal to maintain the OFF state of the first PMOS switching element using a voltage at a source of the first PMOS switching element and a voltage at a drain of the first PMOS switching element; the PA power supply provides a first PA power supply signal; and the first ET power supply provides a first ET power supply signal, such that the first PA power supply signal is based on the first ET power supply signal.

First claim

What is claimed is:

1. A power amplifier (PA) power supply comprising a first PA connection node, a first envelope tracking (ET) power supply, a second power supply, power supply control circuitry, a first P-type metal oxide semiconductor (PMOS) switching element, and a second PMOS switching element, wherein:
the PA power supply is configured to:
operate in one of a plurality of operating modes; and
during a first operating mode of the plurality of operating modes, provide a first PA power supply signal via the first PA connection node;

the first PMOS switching element is coupled between the second power supply and the first PA connection node;
the second PMOS switching element is coupled between the first ET power supply and the first PA connection node; and
during the first operating mode, the power supply control circuitry is configured to:
select an OFF state of the first PMOS switching element using a first switch control signal; and
adjust a voltage of the first switch control signal to maintain the OFF state of the first PMOS switching element using a voltage at a source of the first PMOS switching element and a voltage at a drain of the first PMOS switching element.

2. The PA power supply of claim 1 wherein during the first operating mode:
the first ET power supply is configured to provide a first ET power supply signal, such that the first PA power supply signal is based on the first ET power supply signal; and
the power supply control circuitry is further configured to select an ON state of the second PMOS switching element using a second switch control signal.

3. The PA power supply of claim 1 wherein a propagation delay in transitioning the first PMOS switching element from an ON state to the OFF state is less than eight nanoseconds.

4. The PA power supply of claim 1 wherein during the first operating mode, a bandwidth of the first PA power supply signal is greater than 15 megahertz.

5. The PA power supply of claim 1 wherein during the first operating mode, the power supply control circuitry is further configured to adjust the voltage of the first switch control signal to maintain the OFF state of the first PMOS switching element using a highest one of the voltage at the source of the first PMOS switching element and the voltage at the drain of the first PMOS switching element.

6. The PA power supply of claim 1 wherein during the first operating mode, the power supply control circuitry is further configured to adjust the voltage of the first switch control signal to maintain the OFF state of the first PMOS switching element using a highest one of the voltage at the source of the first PMOS switching element, the voltage at the drain of the first PMOS switching element, and a DC source voltage.

7. The PA power supply of claim 1 , wherein the second power supply comprises a second ET power supply.

8. The PA power supply of claim 7 wherein during the first operating mode:
the power supply control circuitry is further configured to select an ON state of the second PMOS switching element using a second switch control signal;
the first ET power supply is configured to provide a first ET power supply signal, such that the first PA power supply signal is based on the first ET power supply signal; and
the second ET power supply is configured to provide a second ET power supply signal, such that a second PA power supply signal is based on the second ET power supply signal.

9. The PA power supply of claim 8 wherein during the first operating mode:
a first RF PA is configured to receive and amplify a first RF input signal to provide a first RF transmit signal using the first PA power supply signal;
a second RF PA is configured to receive and amplify a second RF input signal to provide a second RF transmit signal using the second PA power supply signal; and
the first RF transmit signal and the second RF transmit signal are transmit uplink carrier aggregation signals.

10. The PA power supply of claim 7 wherein during a second operating mode of the plurality of operating modes:
the power supply control circuitry is further configured to select an ON state of the first PMOS switching element using the first switch control signal and select an OFF state of the second PMOS switching element using a second switch control signal;
the first ET power supply is configured to provide a first ET power supply signal, such that a third PA power supply signal is based on the first ET power supply signal; and
the second ET power supply is configured to provide a second ET power supply signal, such that the first PA power supply signal is based on the second ET power supply signal.

11. The PA power supply of claim 10 wherein during the second operating mode, the power supply control circuitry is further configured to adjust a voltage of the second switch control signal to maintain the OFF state of the second PMOS switching element using a highest one of a voltage at a source of the second PMOS switching element and a voltage at a drain of the second PMOS switching element.

12. The PA power supply of claim 10 wherein during the second operating mode, the power supply control circuitry is further configured to adjust a voltage of the second switch control signal to maintain the OFF state of the second PMOS switching element using a highest one of a voltage at a source of the second PMOS switching element, a voltage at the drain of the second PMOS switching element, and a DC source voltage.

13. The PA power supply of claim 1 further comprising a first N-type metal oxide semiconductor (NMOS) switching element and a second NMOS switching element, wherein:
the first NMOS switching element is coupled across the first PMOS switching element and the second NMOS switching element is coupled across the second PMOS switching element; and
during the first operating mode, the power supply control circuitry is further configured to select an OFF state of the first NMOS switching element using a first NMOS switch control signal and select an ON state of the second NMOS switching element using a second NMOS switch control signal, such that the second NMOS switching element is configured to assist the second PMOS switching element.

14. The PA power supply of claim 2 further having a second PA connection node and further comprising, a third PMOS switching element, and a fourth PMOS switching element, wherein:
the second power supply comprises an average power tracking power supply;
the first PMOS switching element is further coupled between the average power tracking power supply and the first PA connection node;
the third PMOS switching element is coupled between the average power tracking power supply and the second PA connection node;
the fourth PMOS switching element is coupled between the first ET power supply and the second PA connection node;
during the first operating mode, the average power tracking power supply is configured to provide an average power tracking power supply signal, such that a second PA power supply signal is based on the average power tracking power supply signal; and
during the first operating mode, the power supply control circuitry is further configured to select an ON state of the third PMOS switching element using a third switch control signal and select an OFF state of the fourth PMOS switching element using a fourth switch control signal.

15. The PA power supply of claim 14 wherein during a second operating mode of the plurality of operating modes:
the power supply control circuitry is further configured to:
select an ON state of the first PMOS switching element using th

Assignees

• Qorvo Us Inc

Inventors

• Nag Manbir Singh
• Kay Michael R
• Gorisse Philippe
• Khlat Nadim

Classifications

• H03F3/245

  with semiconductor devices only · CPC title

• H03F2200/105

  A non-specified detector of the power of a signal being used in an amplifying circuit · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03F3/193

  with field-effect devices (H03F3/195 takes precedence) · CPC title

• H04W52/52

  using AGC [Automatic Gain Control] circuits or amplifiers · CPC title