Semiconductor device and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-10079305-B2
Application number	US-201514861748-A
Country	US
Kind code	B2
Filing date	Sep 22, 2015
Priority date	Sep 23, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate provided with an elongated active pattern, the active pattern including a recess and first and second active fins, the recess having a first side surface defined by a sidewall of the first active fin, a second side surface defined by a sidewall of the second active fin, and a bottom surface between the first and second side surfaces;
an epitaxial source/drain region in the recess, the epitaxial source/drain region comprising a first epitaxial layer covering the first and second side surfaces and the bottom surface of the recess, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer; and
a gate electrode extending across the first fin,
wherein the first, second and third epitaxial layers each comprise a compound semiconductor material comprised of a first semiconductor element and a second semiconductor element and are each doped with a charge carrier impurity,
wherein a thickness of the second epitaxial layer increases gradually from the first side surface of the recess to reach a maximum value on the bottom surface of the recess, then decreases gradually toward the second side surface of the recess,
wherein the atomic percentage of the second semiconductor element in the first epitaxial layer is less than the atomic percentage of the second semiconductor element in the second epitaxial layer and less than the atomic percentage of the second semiconductor element in the third epitaxial layer, and
wherein a concentration of charge carrier impurity in the second epitaxial layer is higher than a concentration of the charge carrier impurity in the third epitaxial layer.

2. The semiconductor device of claim 1 , wherein the active pattern comprises the first semiconductor element.

3. The semiconductor device of claim 1 , wherein a concentration of charge carrier impurity in the first epitaxial layer is lower than a concentration of the charge carrier impurity in the second epitaxial layer and lower than a concentration of the charge carrier impurity in the third epitaxial layer.

4. The semiconductor device of claim 1 , wherein the first and second semiconductor elements are group IV type semiconductor materials.

5. The semiconductor device of claim 1 , wherein the epitaxial source/drain region comprises a portion of a first source/drain region, the first source/drain region also comprising an impurity diffusion source/drain portion comprising portions of the active pattern located under the gate electrode with the charge carrier impurity diffused therein, the portions of the active pattern with the charge carrier impurity extending along a side of the recess from the bottom surface of the recess to a top of the recess.

6. The semiconductor device of claim 1 , wherein the second epitaxial layer is thicker than the first epitaxial layer.

7. A semiconductor device, comprising:
an active pattern protruding from a substrate, the active pattern comprising a recess having a bottom surface and side surfaces that face each other and having a curved profile in a cross sectional view taken in a first direction parallel to a length direction of the active pattern;
first and second gate structures crossing the active pattern and extending in a second direction crossing the first direction, each of the first and second gate structures comprising a gate electrode and a gate spacer on a sidewall of the gate electrode, the first gate structure being adjacent to the second gate structure with the recess of the active pattern positioned between the first gate structure and the second gate structure;
a source/drain epitaxial layer in the recess, the source/drain epitaxial layer including a first portion in contact with the active pattern, a second portion extending from the first portion, and a third portion extending from the second portion; and
a pair of sidewall spacers formed directly on both sidewalls of the first portion of the source/drain epitaxial layer,
wherein, in a vertical cross sectional view taken in the second direction, a width of the second portion in the second direction increases in an upward direction and a width of the third portion in the second direction decreases in the upward direction,
wherein the pair of sidewall spacers are spaced apart from each other in the second direction,
wherein the source/drain region comprises a source/drain epitaxial layer formed in the recess, wherein the source/drain epitaxial layer comprise a first epitaxial layer in contact with the bottom and side surfaces of the recess, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer,
wherein the first to third epitaxial layers are doped with the same impurities, and
wherein the third epitaxial layer has an impurity concentration that is higher than that of the first epitaxial layer and lower than that of the second epitaxial layer.

8. The semiconductor device of claim 7 ,
wherein the active pattern comprises first and second active fins respectively positioned below the first and second gate structures, and
wherein the side surfaces of the recess are defined by sidewalls of the first and second active fins.

9. The semiconductor device of claim 8 , wherein each of the side surfaces of the recess comprises a first side surface and a second side surface,
wherein a width of the recess between the first side surfaces increases in a downward direction, and
wherein a width of the recess between the second side surfaces decreases in the downward direction.

10. The semiconductor device of claim 7 , wherein a thickness of a lowermost portion of the second epitaxial layer on the bottom surface is greater than a thickness of a lowermost portion of the first epitaxial layer.

11. The semiconductor device of claim 7 , further comprising:
device isolation patterns provided on the substrate at opposite sides of the active pattern,
wherein the pair of sidewall spacers vertically overlap the device isolation patterns.

12. The semiconductor device of claim 7 , wherein each of the first to third epitaxial layers contains germanium, and germanium concentrations of the second and third epitaxial layers are higher than that of the first epitaxial layer.

13. The semiconductor device claim 7 , wherein the source/drain epitaxial layer further comprises a fourth epitaxial layer on the third epitaxial layer, and the fourth epitaxial layer comprises a silicon layer.

14. A semiconductor device, comprising:
a substrate provided with an elongated active pattern, the active pattern including a recess and first and second active fins including sidewalls defining at least portions of the recess;
an epitaxial source/drain region in the recess, the epitaxial source/drain region comprising a first epitaxial layer a bottom surface of the recess, a second epitaxial layer on the first epitaxial layer, and a third epitaxial layer on the second epitaxial layer; and
a gate electrode extending across the first active fin and along sidewalls of the first active fin,
wherein the first, second and third epitaxial layers each comprise a compound semiconductor material comprised of a first semiconductor element and a second semiconductor element and are each doped with a charge carrier impurity,
wherein the third epitaxial layer has a width in a second direction, the width increases gradually from a top portion of the second epitaxial layer to reach a maximum value between the top portion of the second epitaxial layer and a bottom surface of the third epitaxial layer, then decreases toward the bottom s

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Byeongchan
• Kim Nam-Kyu
• Kim Jinbum
• Lee Kwan Heum
• Lee Choeun
• Jung Sujin

Classifications

• H01L29/7851 Primary

  Electricity · mapped topic

• H01L29/0847

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H01L29/165

  Electricity · mapped topic