Method of fabricating metal-insulator-metal capacitor

Patent metadata

Field	Value
Publication number	US-10079277-B2
Application number	US-201615362771-A
Country	US
Kind code	B2
Filing date	Nov 28, 2016
Priority date	Nov 28, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A method of fabricating a metal-insulator-metal capacitor includes providing a dielectric layer. The dielectric layer is etched to form a first hole including a first convex profile bulging into the dielectric layer. Subsequently, the dielectric layer is etched to form a second hole including a second convex profile bulging into the dielectric layer. A first metal layer is formed to conformally cover the capacitor trench. An insulating layer is formed to cover the first metal layer. Finally, a second metal layer is formed covering the insulating layer.

First claim

What is claimed is:

1. A method of fabricating a metal-insulator-metal (MIM) capacitor, comprising:
providing a dielectric layer, wherein the dielectric layer comprises un-doped silicon oxide, doped silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride or silicon carbon nitride, and wherein the dielectric layer comprises a first dielectric layer and a second dielectric layer, and an etching rate of the first dielectric layer and an etching rate of the second dielectric layer are different with respect to a same etchant;
forming a capacitor trench within the dielectric layer, wherein the method of forming the capacitor trench comprises the steps of:
etching the dielectric layer to form a first hole comprising a first convex profile bulging into the dielectric layer; and
etching the dielectric layer to form a second hole comprising a second convex profile bulging into the dielectric layer, wherein the second hole connects to the first hole, the first convex profile comprises a first curvature, the second convex profile comprises a second curvature, and the first curvature is different from the second curvature, the first hole is within the first dielectric layer and the second hole is within the second dielectric layer;

forming a first metal layer conformally covering the capacitor trench;
forming an insulating layer covering the first metal layer; and
forming a second metal layer covering the insulating layer.

2. The method of fabricating a MIM capacitor of claim 1 , wherein the method of forming the capacitor trench further comprises repeating the step of forming the first hole.

3. The method of fabricating a MIM capacitor of claim 1 , wherein the method of forming the capacitor trench further comprising repeating the step of forming the second hole.

4. The method of fabricating a MIM capacitor of claim 1 , wherein the first convex profile comprises a first curvature, the second convex profile comprises a second curvature, and the first curvature is the same as the second curvature.

5. The method of fabricating a MIM capacitor of claim 4 , wherein the dielectric layer is a single layer consisting of a single type of material.

6. The method of fabricating a MIM capacitor of claim 1 , wherein the first dielectric layer comprises dopants of a first concentration, the second dielectric layer comprises dopants of a second concentration, the first dielectric layer and the second dielectric layer comprise the same material.

7. The method of fabricating a MIM capacitor of claim 6 , wherein the first concentration is zero, the second concentration has a gradient decreasing from the middle of the second dielectric layer to the top of the second dielectric layer.

8. The method of fabricating a MIM capacitor of claim 6 , wherein the first concentration and the second concentration are different.

9. The method of fabricating a MIM capacitor of claim 1 , wherein first dielectric layer and the second dielectric layer comprises the same material, the first dielectric layer is formed by a plurality of first fabricating parameters, the second dielectric layer is formed by a plurality of second fabricating parameters, at least one of the first fabricating parameters is different from at least one of the second fabricating parameters.

10. The method of fabricating a MIM capacitor of claim 1 , wherein steps of forming the first hole and the second hole comprise:
etching the first dielectric layer and the second dielectric layer to form a trench; and
after forming the trench, etching the first dielectric layer and the second dielectric layer simultaneously at different etching rates to form the first hole and the second hole.

11. The method of fabricating a MIM capacitor of claim 1 , wherein the second hole is below the first hole.

12. The method of fabricating a MIM capacitor of claim 1 , wherein steps of forming the first hole and the second hole comprise:
performing an isotropic etching process on the dielectric layer to form the first hole;
forming a liner covering an inner wall of the first hole;
after forming the first hole, performing the isotropic etching process to the bottom of the first hole and etching the dielectric layer to form the second hole; and
removing the liner after forming the second hole.

Assignees

• United Microelectronics Corp

Inventors

• Yew Tri-Rung
• Lin Hung-Chan
• Feng li-wei
• Ho Chien-Ting
• Chang Chia-Lung

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10P14/412

  Deposition of metallic or metal-silicide materials · CPC title

• H01L28/82 Primary

  Electricity · mapped topic

• H01L21/31111

  Electricity · mapped topic