Logic and flash field-effect transistors

Patent metadata

Field	Value
Publication number	US-10079242-B2
Application number	US-201615366425-A
Country	US
Kind code	B2
Filing date	Dec 1, 2016
Priority date	Dec 1, 2016
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

Methods of forming a device structure for a field-effect transistor and device structures for a field-effect transistor. A first gate dielectric layer is formed on a semiconductor layer in a first area. A hardmask layer is formed on the first gate dielectric layer in the first area of the semiconductor layer. A gate stack layer is formed on the semiconductor layer in a second area and on the hardmask layer in the first area of the semiconductor layer. The hardmask layer separates the gate stack layer from the first gate dielectric layer on the first area of the semiconductor layer.

First claim

What is claimed is:

1. A method comprising:
forming a first gate dielectric layer on a semiconductor layer in a first area;
depositing a silicon-germanium layer on a section of the semiconductor layer in a second area;
oxidizing the silicon-germanium layer to transport germanium from the silicon-germanium layer into the section of the semiconductor layer in the second area;
after oxidizing the silicon-germanium layer, forming a hardmask layer over the first gate dielectric layer in the first area of the semiconductor layer; and
forming a gate stack layer over the second area of the semiconductor layer and on the hardmask layer in the first area of the semiconductor layer,
wherein the hardmask layer separates the gate stack layer from the first gate dielectric layer on the semiconductor layer in the first area.

2. The method of claim 1 wherein the silicon-germanium layer is oxidized after the first gate dielectric layer is formed.

3. The method of claim 2 wherein the first gate dielectric layer is formed on the semiconductor layer in the second area, and further comprising:
before oxidizing the silicon-germanium layer, removing the first gate dielectric layer from the section of the semiconductor layer in the second area.

4. The method of claim 3 wherein the silicon-germanium layer is converted to a silicon dioxide layer by the oxidation, and further comprising:
reducing a thickness of the silicon dioxide layer; and
after the thickness is reduced, forming a gate structure of a field-effect transistor from the gate stack layer on the silicon dioxide layer.

5. The method of claim 1 wherein the silicon-germanium layer is oxidized before the first gate dielectric layer is formed.

6. The method of claim 5 wherein the silicon-germanium layer is converted to a silicon dioxide layer by the oxidation, and further comprising:
removing the silicon dioxide layer,
wherein the first gate dielectric layer is formed on the section of the semiconductor layer in the second area.

7. The method of claim 5 further comprising: forming a gate structure of a field-effect transistor from the gate stack layer on the first gate dielectric layer.

8. The method of claim 1 further comprising:
before the hardmask layer is formed, forming a second gate dielectric layer on the first gate dielectric layer and a third gate dielectric layer on the second gate dielectric layer.

9. The method of claim 8 wherein the first gate dielectric layer is comprised of silicon dioxide, the second gate dielectric layer is comprised of silicon nitride, and the third gate dielectric layer is comprised of silicon dioxide.

10. The method of claim 1 further comprising:
after the first gate dielectric layer is formed, forming a trench isolation region in the semiconductor layer and extending through the hardmask layer.

11. The method of claim 10 wherein the hardmask layer is formed before the trench isolation region is formed and masks the first dielectric layer during the formation of the trench isolation region.

12. The method of claim 1 further comprising:
removing the gate stack layer and the hardmask layer from the first area of the semiconductor layer; and
forming a gate structure of a field-effect transistor over the first gate dielectric layer in the first area of the semiconductor layer.

13. The method of claim 1 further comprising:
forming a gate structure of a field-effect transistor from the gate stack layer over the second area of the semiconductor layer.

14. The method of claim 1 wherein the first gate dielectric layer is formed on the second area of the semiconductor layer, and further comprising:
removing the first gate dielectric layer from the second area of the semiconductor layer before the gate stack layer is formed.

15. The method of claim 1 wherein the first gate dielectric layer is formed on the second area of the semiconductor layer, and the gate stack layer is formed on the first gate dielectric layer in the second area of the semiconductor layer.

16. The method of claim 1 wherein the first gate dielectric layer is formed on the second area of the semiconductor layer, and further comprising:
before the hardmask layer is formed, forming a second gate dielectric layer on the first gate dielectric layer in the first area of the semiconductor layer and in the second area of the semiconductor layer.

17. The method of claim 16 further comprising:
after the hardmask layer is formed, removing the second gate dielectric layer from the second area of the semiconductor layer; and
before the gate stack layer is formed, thinning the first gate dielectric layer in the second area of the semiconductor layer to form an interface layer between the semiconductor layer and the gate stack layer.

18. The method of claim 1 wherein the semiconductor layer is a device layer of a silicon-on-insulator substrate.

19. The method of claim 1 wherein the gate stack layer includes a metal gate layer and a high-k dielectric layer.

Assignees

• Globalfoundries Inc

Inventors

• Richter Ralf
• Melde Thomas
• Erben Elke

Classifications

• H01L29/518

  Electricity · mapped topic

• H01L21/28185

  Electricity · mapped topic

• H01L21/0332

  Electricity · mapped topic

• H01L21/28282

  Electricity · mapped topic

• H01L21/02532

  Electricity · mapped topic