Methods of fabricating an electronic package structure

US10079190B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10079190-B2
Application numberUS-201514801173-A
CountryUS
Kind codeB2
Filing dateJul 16, 2015
Priority dateNov 10, 2014
Publication dateSep 18, 2018
Grant dateSep 18, 2018

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

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  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring layer, and forming an encapsulating layer to cover the electronic component, thereby allowing the single wiring layer to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path. The present invention further provides a package structure thus fabricated.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a package structure, comprising: providing a conductive layer having opposing first and second sides; removing a portion of the first side of the conductive layer to form a plurality of openings on the first side of the conductive layer; forming an insulative material in the openings, allowing the insulative material to be an insulative layer that has a first surface, from which the first side of the conductive layer is exposed, and a second surface opposing the first surface; removing a portion of the second side of the conductive layer to allow the conductive layer to serve as a wiring layer, with the second surface of the insulative layer exposed from the second side of the wiring layer; right after removing the portion of the second side of the conductive layer to allow the conductive layer to serve as the wiring layer, disposing directly on the second side of the wiring layer at least one electronic component that is electrically connected to the wiring layer; and forming on the second side of the wiring layer and the second surface of the insulative layer an encapsulating layer that encapsulates and is in direct contact with the at least one electronic component. 2. The method of claim 1 , wherein the second side of the wiring layer is electrically connected to the electronic component, and the first side of the wiring layer is defined to have a plurality of conductive pads thereon. 3. The method of claim 1 , wherein the first side of the wiring layer is flush with the first surface of the insulative layer. 4. The method of claim 1 , wherein the electronic component is an active component, a passive component, or a combination thereof. 5. The method of claim 1 , wherein the electronic component is electrically connected to the wiring layer in a flip-chip manner. 6. The method of claim 1 , further comprising forming on the first surface of the insulative layer a plurality of conductive elements that are electrically connected to the first side of the wiring layer. 7. A method of fabricating a package structure, comprising: providing a conductive layer having opposing first and second sides; removing a portion of the first side of the conductive layer to form a plurality of openings on the first side of the conductive layer; forming an insulative layer to completely encapsulate the first side of the conductive layer, the insulative layer having opposing first and second surfaces; removing a portion of the insulative layer, with the first side of the conductive layer exposed from the first surface of the insulative layer; after removing the portion of the insulative layer, removing a portion of the second side of the conductive layer to allow the conductive layer to serve as a wiring layer, with the second surface of the insulative layer exposed from the second side of the conductive layer; right after removing the portion of the second side of the conductive layer to allow the conductive layer to serve as the wiring layer, disposing directly on the second side of the conductive layer at least one electronic component that is electrically connected to the conductive layer; and forming on the second side of the conductive layer and the second surface of the insulative layer an encapsulating layer that encapsulates and is in direct contact with the electronic components.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • characterised by the relative positions of pads or connectors relative to package parts · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

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Frequently asked questions

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What does patent US10079190B2 cover?
A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring l…
Who is the assignee on this patent?
Phoenix Pioneer Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10W74/117. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 18 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).