Scan driver, display device, and method of driving display device

Patent metadata

Field	Value
Publication number	US-10078983-B2
Application number	US-201615293817-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 23, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and first and second scan signals output from the scan signal generation circuit.

First claim

What is claimed is:

1. A display device comprising:
a display panel displaying an image; and
a scan driver having a scan signal generation circuit on a first side of the display panel and an emission signal generation circuit on a second side of the display panel,
wherein the emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and first and second scan signals output from the scan signal generation circuit,
wherein the emission signal generation circuit comprises:
a first circuit having first and second transistors to charge and discharge a Q node;
a second circuit having third to fifth transistors to charge and discharge a QB node;
a third circuit having a sixth transistor to stabilize an output terminal of the emission signal generation circuit; and
a fourth circuit having a pull-up transistor and first and second pull-down transistors to output a Logic High emission signal or a Logic Low emission signal through an output terminal of the emission signal generation circuit.

2. The display device of claim 1 , wherein
the third transistor configured to charge the QB node to a gate high voltage in response to the second scan signal of the scan signal generation circuit;
the fourth transistor configured to reset the QB node using a reset signal in response to the first scan signal of the scan signal generation circuit; and
the fifth transistor configured to discharge the QB node to a gate low voltage in response to an N-th clock signal.

3. The display device of claim 1 , wherein
the third transistor configured such that a gate electrode thereof is connected to an output terminal of an (N−x)-th shift register of the scan signal generation circuit (where x is an integer equal to or greater than 1), a first electrode thereof is connected to a gate high voltage line, and a second electrode thereof is connected to the QB node;
the fourth transistor configured such that a gate electrode thereof is connected to an output terminal of an N-th shift register of the scan signal generation circuit, a first electrode thereof is connected to a reset signal line, and a second electrode thereof is connected to the QB node; and
the fifth transistor configured such that a gate electrode thereof is connected to an N-th clock signal line, a first electrode thereof is connected to a gate low voltage line, and a second electrode thereof is connected to the QB node.

4. The display device of claim 1 , wherein
the sixth transistor configured such that a gate electrode thereof is connected to the output terminal of the emission signal generation circuit, a first electrode thereof is connected to a gate high voltage line, and a second electrode thereof is connected to a node located between a first electrode of the first pull-down transistor and a second electrode of the second pull-down transistor.

5. The display device of claim 4 , wherein the third circuit comprises a first capacitor configured such that one end thereof is connected to the Q node and the other end thereof is connected to the output terminal of the emission signal generation circuit.

6. The display device of claim 5 , wherein the third circuit comprises:
a second capacitor configured such that one end thereof is connected to a gate electrode of the second pull-down transistor and the other end thereof is connected to a gate low voltage line; and
a seventh transistor configured such that a gate electrode thereof is connected to the gate high voltage line, a first electrode thereof is connected to one side of the Q node being adjacent to the first electrode of the first transistor, and a second electrode thereof is connected to the other side of the Q node being adjacent to the one end of the first capacitor.

7. The display device of claim 1 , wherein each of the first scan signal, the second scan signal, and the emission signal has a first signal with a Logic High section and a second signal with a Logic High section, wherein the second signal with the Logic High section is longer than the Logic High section of the first signal.

8. A scan driver for a display panel, comprising:
a scan signal generation circuit on a first side of the display panel; and
an emission signal generation circuit on a second side of the display panel,
wherein the emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and first and second scan signals output from the scan signal generation circuit,
wherein the emission signal generation circuit comprises:
a first circuit having first and second transistors to charge and discharge a Q node;
a second circuit having third to fifth transistors to charge and discharge a QB node;
a third circuit having a sixth transistor to stabilize an output terminal of the emission signal generation circuit; and
a fourth circuit configured to comprise a pull-up transistor and first and second pull-down transistors to output a Logic High emission signal or a Logic Low emission signal through an output terminal of the emission signal generation circuit.

9. The scan driver of claim 8 , wherein
the third transistor configured such that a gate electrode thereof is connected to an output terminal of an (N−x)-th shift register of the scan signal generation circuit (where x is an integer equal to or greater than 1), a first electrode thereof is connected to a gate high voltage line, and a second electrode thereof is connected to the QB node;
the fourth transistor configured such that a gate electrode thereof is connected to an output terminal of an N-th shift register of the scan signal generation circuit, a first electrode thereof is connected to a reset signal line, and a second electrode thereof is connected to the QB node; and
the fifth transistor configured such that a gate electrode thereof is connected to an N-th clock signal, a first electrode thereof is connected to a gate low voltage line, and a second electrode thereof is connected to the QB node.

Assignees

• Lg Display Co Ltd

Inventors

• Lee Jungmin
• Bong Junho

Classifications

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2310/0262

  The addressing of the pixel, in a display other than an active matrix LCD, involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependent on signals of two data electrodes · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title