Data propagation analysis for debugging a circuit design

Patent metadata

Field	Value
Publication number	US-10078714-B2
Application number	US-201315033643-A
Country	US
Kind code	B2
Filing date	Oct 31, 2013
Priority date	Oct 31, 2013
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A method for data propagation analysis. A data propagation diagram for a circuit design is generated. The data propagation diagram includes a plurality of nodes and a plurality of edges connecting the nodes. The nodes represent data locations in the circuit design and the edges represent data propagation paths between the data locations in the circuit design. A signal trace specifying signal values for the circuit design is analyzed to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle. A visual animation is displayed on the data propagation diagram indicating movement of the data between a first node of the nodes corresponding to the first data location and a second node of the nodes corresponding to the second data location.

First claim

What is claimed is:

1. A computer-implemented method for debugging a circuit design with a data propagation analysis, comprising:
identifying a plurality of circuit component designs in a circuit design;
reducing, at a plurality of modules stored at least partially in memory of and functioning in conjunction with at least one microprocessor of one or more computing systems, the plurality of circuit component designs into a reduced set of circuit component designs representing data locations in the circuit design at least by omitting one or more circuit component designs from the circuit design;
generating, at a diagram generation module in the plurality of modules, a data propagation diagram for the circuit design for representing the reduced set of circuit component designs as a plurality of nodes, the data propagation diagram including a plurality of edges connecting the plurality of nodes;
analyzing, at the plurality of modules, a signal trace specifying at least one signal value for the circuit design to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle; and
in response to determining that the data at the first data location is causally related to the data at the second data location, executing an animation module of the plurality of modules that generates and displays a visual animation on the data propagation diagram in the user interface indicating movement of the data between a first node of the plurality of nodes corresponding to the first data location and a second node of the plurality of nodes corresponding to the second data location.

2. The method of claim 1 , further comprising:
receiving a plurality of source locations and a plurality of destination locations in the circuit design,
wherein the data propagation diagram is generated based on the plurality of source locations and the plurality of destination locations.

3. The method of claim 1 , wherein analyzing the signal trace comprises:
identifying, based on the signal trace for the circuit design, the first data location of the data locations having the data during the first clock cycle; and
determining, based on the signal trace for the circuit design, whether the data at the first data location of the data locations during the first clock cycle is causally related to the data at the second data location of the data locations during the second clock cycle.

4. The method of claim 3 , wherein the first data location and the second data location are separated by a routing control circuit controlled by a control input, and determining whether the data at the first data location during the first clock cycle is causally related to the data at the second data location comprises:
determining, based on a value of the control input in the signal trace, whether the data at the first data location is causally related to the data at a second data location of the data locations during the second clock cycle.

5. The method of claim 1 , wherein the first clock cycle is before the second clock cycle, and analyzing the signal trace comprises:
analyzing the signal trace to determine whether the data at the first data location causes the data at the second data location.

6. The method of claim 1 , wherein the second clock cycle is before the first clock cycle, and analyzing the signal trace comprises:
analyzing the signal trace to determine whether the data at the first data location is caused by the data at the second data location.

7. The method of claim 1 , wherein displaying the visual animation comprises displaying a forward visual animation indicating movement of the data in a forward time dimension.

8. The method of claim 1 , wherein displaying the visual animation comprises displaying a backward visual animation indicating movement of the data in a backward time dimension.

9. The method of claim 1 , wherein displaying the visual animation comprises:
displaying a first visual cue on the data propagation diagram highlighting the first node of the data propagation diagram corresponding to the first data location of the circuit design; and
after displaying the first visual cue, displaying a second visual cue on the data propagation diagram highlighting the second node of the data propagation diagram corresponding to the second data location of the circuit design.

10. The method of claim 1 , further comprising:
displaying a waveform of the trace in conjunction with the visual animation indicating movement of the data between the first node of the plurality of nodes corresponding to the first data location and the second node of the plurality of nodes corresponding to the second data location; and
highlighting one or more portions of the waveform that correspond to the visual animation indicating movement of the data between the first node of the plurality of nodes corresponding to the first data location and the second node of the plurality of nodes corresponding to the second data location.

11. A non-transitory computer readable medium storing code for circuit design analysis, the code comprising instructions for:
identifying a plurality of circuit component designs in a circuit design;
reducing, at a plurality of modules stored at least partially in memory of and functioning in conjunction with at least one microprocessor of one or more computing systems, the plurality of circuit component designs into a reduced set of circuit component designs representing data locations in the circuit design at least by omitting one or more circuit component designs from the circuit design;
generating, at a diagram generation module in the plurality of modules, a data propagation diagram for the circuit design for representing the reduced set of circuit component designs as a plurality of nodes, the data propagation diagram including a plurality of edges connecting the plurality of nodes;
analyzing, at the plurality of modules, a signal trace specifying at least one signal value for the circuit design to determine whether data at a first data location of the data locations during a first clock cycle is causally related to the data at a second data location of the data locations during a second clock cycle; and
in response to determining that the data at the first data location is causally related to the data at the second data location, executing an animation module of the plurality of modules that generates and displays a visual animation on the data propagation diagram in the user interface indicating movement of the data between a first node of the plurality of nodes corresponding to the first data location and a second node of the plurality of nodes corresponding to the second data location.

12. The computer readable medium of claim 11 , the code comprising further instructions for:
receiving a plurality of source locations and a plurality of destination locations in the circuit design,
wherein the data propagation diagram is generated based on the plurality of source locations and the plurality of destination locations.

13. The computer readable medium of claim 11 , wherein analyzing the signal trace comprises:
identifying, based on the signal trace for the circuit design, first data location of the data locations having the data during the first clock cycle; and
determining, based on the signal trace for the circuit design, whether the data at the first data location of the data locations during the first clock cycle is causally related to the data at the second data location of the data locations during the second clock cycle.

Assignees

• Peixoto Fabiano
• Guimaraes Breno Rodrigues
• Sun Xiaoyang
• Coelho Jr Claudionor
• Cadence Design Systems Inc

Inventors

• Peixoto Fabiano
• Guimaraes Breno Rodrigues
• Sun Xiaoyang
• Coelho Jr Claudionor

Classifications

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/35 Primary

  Delay-insensitive circuit design, e.g. asynchronous or self-timed · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/3312

  Timing analysis · CPC title

• G06F30/396

  Clock trees · CPC title