Computing in parallel processing environments

Patent metadata

Field	Value
Publication number	US-10078613-B1
Application number	US-201514636296-A
Country	US
Kind code	B1
Filing date	Mar 3, 2015
Priority date	Mar 5, 2014
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A computing system comprises one or more core processors coupled to a communication network among the cores via a switch in each core and switching circuitry to forward data among cores and switches. Features include a programmable classification processor for directing packets, techniques for managing virtual functions on an IO accelerator card, packet scheduling techniques, multi-processor communication using shared FIFOs, programmable duty cycle adjustment and delay adjustment circuits, a new class of instructions that use a ready bit, and cache coherence and memory ordering techniques.

First claim

What is claimed is:

1. A system comprises:
a tiled multicore processor that includes plural processor tiles, the processor tiles comprising a processor coupled to memory and a switch;
a network interface having plural receive and transmit ports; and
a programmable classification processor on the network interface, the programmable classification processor coupled to the plural receive ports, and the programmable classification processor coupled to the processor tiles, and further including:
a processor table memory; and
instruction memory, with instruction memory storing a program that defines rules for packet delivery and switching, and configures the programmable classification processor to:
classify packets received at the plural ports, as either requiring or not requiring processor tile intervention;
cause the programmable classification processor to direct the packets received on the plural receive ports out of any egress port on the programmable classification processor without intervention from any of the processor tiles, for a classification that does not require processor tile intervention.

2. The system of claim 1 wherein the programmable classification processor is disposed between the plural receive ports and the processor tiles.

3. The system of claim 1 , further comprising a processing queue and wherein the programmable classification processor is configured to:
determine whether a packet should be handled by a one of the tile processors; and when the programmable classification processor determines that the packet should be handled by the one of the tile processors, the programmable classification processor,
cause the determined packet to be forwarded to the processing queue for processing by the one of the processor tiles.

4. The system of claim 1 wherein the processor tiles implement exception handling and slow path code execution.

5. The system of claim 1 wherein the programmable classification processor handles fast-path operations.

6. The system of claim 5 wherein fast path operations are on packets that are directed out of any port of the programmable classification processor with minimal latency and processing overhead compared to that of the tiles.

7. The system of claim 1 wherein the processor tiles dynamically direct the programmable classification processor to implement new policies for forwarding and local processing of packets.

8. The system of claim 1 wherein the processor tiles dynamically updates the programmable classification processor in real time.

9. The system of claim 1 wherein the processor tiles implement higher level application and control plane processing without the burden of data plane operations.

10. The system of claim 1 wherein the tile programmable classification processor executes the rules that allow packets to be identified based on their contents and once identified, packets are directed to an egress port of the programmable processor or to one of the processor tiles.

11. The system of claim 1 wherein the processor table memory stores parameters.

12. The system of claim 1 wherein in the rules are updated dynamically by modifying the instruction memory and the processor table memory.

13. A method executed by a tiled multicore processor that includes plural processor tiles, with the processor tiles comprising a processor, memory and a switch, the method comprising:
receiving packets at a network interface; and
classifying received packets by a programmable classification processor, as either requiring or not requiring processor tile intervention, the programmable classification processor having ports and including a processor table memory and instruction memory;
causing the programmable classification processor, to direct the packets received on plural receive ports out of any egress port on the programmable classification processor, without intervention from any of the tile processor tiles for a classification that does not require processor tile intervention.

14. The method of claim 13 wherein the programmable classification processor is disposed between the network ports and the processor tiles on the network interface and classification occurs according to rules defined for packet delivery and switching.

15. The method of claim 14 wherein a rule is a handling rule, and the method further comprises:
configuring the programmable classification processor to determine whether a packet should be handled by a one of the processor tiles; and
causing the determined packet to be forwarded to a processing queue for processing by the one of the processor tiles.

16. The method of claim 14 wherein a rule is a handling rule, and the method further comprises:
determining by the programmable classification processor whether a packet should be handled by a one of the processor tiles; and
causing the determined packet to be forwarded to a processing queue for processing by the one of the processor tiles.

17. The method of claim 13 wherein the tile processors implement exception handling and slow path code execution.

18. The method of claim 13 wherein the programmable classification processor handles fast-path operations.

19. The method of claim 13 wherein fast path operations are on packets that are directed out of any port of the programmable classification processor with minimal latency and processing overhead compared to that of the processor tiles.

20. The method of claim 13 further comprising:
dynamically directing the programmable classification processor to implement new policies for forwarding and local processing of packets.

21. The method of claim 13 further comprising:
dynamically updating the programmable classification processor in real time.

22. The method of claim 13 wherein the tile processors intervene to implement higher level application and control plane processing operations.

23. The method of claim 13 further comprising:
executing by the programmable classification processor, rules that allow packets to be classified based on identified contents.

24. The method of claim 13 , further comprising:
dynamically updating the programmable classification processor in real time and wherein the programmable classification processor, modifies software and the tables, and
queuing incoming packets during updating of the software.

25. The method of claim 13 further comprising:
updating rules in the programmable classifier processor rules dynamically by modifying the instruction memory and the processor table memory.

26. A computer program product tangibly stored in non-transitory media the computer program product for a system including a tiled multicore processor that includes plural processor tiles, with the processor tiles comprising a processor, memory and a switch, the computer program product comprising instructions to cause a processor to:
receive packets at a network interface; and
classify the received packets as either requiring or not requiring processor tile intervention, by a programmable classification processor having ports and including a processor table memory and instruction memory;
direct packets out of any port on the programmable classification processor, without intervention from any of the plural processor tiles, for a classification that does not require processor tile intervention.

27. The computer program product of claim 26 further comprising instru

Assignees

• Ramey Carl G
• Mellanox Technologies Ltd

Inventors

• Ramey Carl G

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title