Apparatus and method for vector-based signal routing

Patent metadata

Field	Value
Publication number	US-10078600-B2
Application number	US-201313926629-A
Country	US
Kind code	B2
Filing date	Jun 25, 2013
Priority date	Jun 25, 2013
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

An apparatus includes a memory, and a control circuit. The memory stores a vector that identifies a signal that is to be provided by an input/output (I/O) interface to a peripheral and indicates a time value. The control circuit is adapted to process the vector and route the identified signal to the peripheral and regulate a time that the signal is routed to the peripheral based on the time value.

First claim

What is claimed is:

1. An apparatus comprising:
a memory to store data representing a plurality of vectors, wherein each vector of the plurality of vectors comprises a distribution field identifying an associated set of input/outputs (I/Os) of an input/output (I/O) interface for communicating with a plurality of peripherals and a time value field identifying an associated time value; and
a control circuit adapted to:
process the plurality of vectors in a sequence; and
in response to processing each vector of the plurality of vectors, communicate a plurality of signals with a set of peripherals of the plurality of peripherals using the associated set of I/Os identified by the distribution field of the vector being processed and regulate a time that communication of the plurality of signals occurs based on the associated time value identified by the time value field of the vector being processed.

2. The apparatus of claim 1 , further comprising a signal conditioning circuit, associated with a first peripheral of the set of peripherals, and adapted to be programmed to condition at least one signal of the plurality of signals to satisfy a specification of the first peripheral.

3. The apparatus of claim 2 , wherein the signal conditioning circuit is adapted to be programmed to modify a timing of the at least one signal.

4. The apparatus of claim 2 , wherein the signal conditioning circuit is adapted to be programmed to asynchronously communicate the at least one signal with the first peripheral.

5. The apparatus of claim 1 , wherein the control circuit is further adapted to be programmed with criteria applied by the control circuit to identify a first part of a given vector of the plurality of vectors associated with the distribution field and a second part of the given vector of the plurality of vectors associated with the time value field.

6. The apparatus of claim 5 , wherein the control circuit is further adapted to read data indicative of the criteria from a designated part of the given vector.

7. The apparatus of claim 5 , wherein the control circuit is further adapted to read data indicative of the criteria from a register.

8. A method comprising:
storing a plurality of vectors, wherein each vector of the plurality of vectors comprises a distribution field identifying an associated set of input/outputs (I/Os) of an input/output (I/O) interface for communicating with a plurality of peripherals and a time value field identifying an associated time value; and
processing the plurality of vectors in a sequence to, for each vector of the plurality of vectors being processed, communicate a plurality of signals with a set of peripherals of the plurality of peripherals using the associated set of I/Os identified by the distribution field of the vector being processed, and regulate a time that communication of the plurality of signals occurs based on the associated time value identified by the time value field of the vector being processed.

9. The method of claim 8 , wherein the storing comprises storing data representing the plurality of vectors in a memory of the I/O interface.

10. The method of claim 8 , further comprising: conditioning at least one signal of the plurality of signals based on a specification of a peripheral of the set of peripherals.

11. The method of claim 10 , wherein the conditioning comprises modifying a timing of a waveform of the at least one signal.

12. The method of claim 11 , wherein modifying the timing comprises modifying a time duration of a pulse of the at least one signal.

13. The method of claim 8 , further comprising programming the I/O interface with criteria to apply to identify a first vector field associated with a given signal of the plurality of signals and a second part vector field associated with a time value for the at least one signal.

14. An apparatus comprising:
a plurality of peripherals;
an integrated circuit comprising an input/output (I/O) interface, wherein the I/O interface comprises a plurality of input/outputs (I/Os);
a memory to store data representing a plurality of vectors, wherein each vector of the plurality of vectors comprises a distribution field identifying an associated set of input/outputs (I/Os) of the plurality of I/Os for communicating with the plurality of peripherals and a time value field identifying an associated time value; and
a control circuit to:
process the plurality of vectors in a sequence; and
in response to processing each vector of the plurality of vectors, communicate a plurality of signals with a set of peripherals of the plurality of peripherals using the associated set of I/Os identified by the distribution field of the vector being processed and regulate a time that communication of the plurality of signals occurs based on the associated time value identified by the time value field of the vector being processed.

15. The apparatus of claim 14 , wherein at least one of the vectors of the plurality of vectors identifies a time value representing a duration for which an associated first signal of the plurality of signals is to be routed to a of the plurality of peripherals.

16. The apparatus of claim 15 , further comprising a signal conditioning circuit associated with a given peripheral of the set of peripherals and adapted to be programmed to condition the first signal to satisfy an associated specification of the given peripheral.

17. The apparatus of claim 16 , wherein the signal conditioning circuit is adapted to be programmed to modify a timing of the first signal.

18. The apparatus of claim 16 , wherein the signal conditioning circuit is adapted to be programmed with a communication protocol used by the given peripheral.

19. The apparatus of claim 15 , wherein the first signal comprises a triggering signal for the given peripheral.

Assignees

• Silicon Lab Inc

Inventors

• Zavalney Paul I
• Wang Xiaohui

Classifications

• G06F13/126 Primary

  and has means for transferring I/O instructions and statuses between control unit and main processor · CPC title