Multiple-core computer processor for reverse time migration

Patent metadata

Field	Value
Publication number	US-10078593-B2
Application number	US-201214354502-A
Country	US
Kind code	B2
Filing date	Oct 26, 2012
Priority date	Oct 28, 2011
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.

First claim

What is claimed is:

1. A multi-core computer processor comprising:
a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture;
a plurality of automatically-managed L1 caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores; and
a plurality of software-managed L1 memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a logically partitioned global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein each logical partition comprises an address space corresponding to one of the plurality of memories, and wherein each of the plurality of processor cores has a one-to-one relationship with a different locality-encoded, non-virtualized address range to a corresponding logical partition, and
wherein at least one of a number of the plurality of processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is selected to optimize a reverse-time-migration (RTM) computation.

2. The multi-core computer processor of claim 1 , further comprising an independent control plane comprising direct message queues between the processor cores, wherein the independent control plane is configured to perform synchronization and enforce memory consistency between the plurality of memories.

3. The multi-core computer processor of claim 1 , wherein the plurality of memories comprises a plurality of local scratch pad memories.

4. The multi-core computer processor of claim 1 , wherein the plurality of memories comprises a plurality of L1 memories.

5. The multi-core computer processor of claim 1 , wherein the plurality of memories comprises a plurality of L2 memories.

6. The multi-core computer processor of claim 1 , wherein the plurality of memories is software-managed and the plurality of caches is automatically managed.

7. The multi-core computer processor of claim 1 , wherein each of the plurality of memories is associated with one and only one of the plurality of processor cores.

8. The multi-core computer processor of claim 1 , wherein the number of the plurality of processor cores is approximately 128.

9. The multi-core computer processor of claim 1 , wherein the size of each of the plurality of caches is 16 kilobytes.

10. The multi-core computer processor of claim 1 , wherein the size of each of the plurality of memories is 256 kilobytes.

11. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores comprises a private 8-kilobyte instruction cache memory.

12. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores comprises a L2 instruction cache memory that is shared among at least one other of the plurality of processor cores.

13. The multi-core computer processor of claim 1 , wherein each of the plurality of processor cores is configured to be able to compute two single-precision floating-point operations per clock cycle of the multi-core computer processor.

14. The multi-core computer processor of claim 13 , wherein each of the plurality of processor cores is configured to execute very long instruction word (VLIW) instructions on a plurality of execution units.

15. The multi-core computer processor of claim 14 , wherein each of the plurality of processor cores is configured to execute 64-bit wide instructions.

16. The multi-core computer processor of claim 1 , wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for modeling a wave equation of the reverse-time-migration (RTM) computation.

17. The multi-core computer processor of claim 1 , wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for modeling a wave equation of the reverse-time-migration (RTM) computation via an 8th or 12th order Laplacian stencil.

18. A method of using a multi-core computer processor, the method comprising:
determining at least one of a number of a plurality of processor cores, a size of each of a plurality of caches, or a size of each of a plurality of memories that optimize a reverse-time-migration (RTM) computation;
storing cache data in at least one of the plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture;
storing memory data in at least one of the plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a logically partitioned global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein each logical partition comprises an address space corresponding to one of the plurality of memories, and wherein each of the plurality of processor cores has a one-to-one relationship with a different locality-encoded, non-virtualized address range to a corresponding logical partition; and
retrieving, by a first processor core of the plurality of processor cores associated with a first memory of the plurality of memories, at least a portion of the memory data, wherein the at least a portion of the memory data is stored in a second memory of the plurality of memories associated with a second processor core of the plurality of processor cores, the second processor core being different from the first processor core and the first memory being different from the second memory.

19. The method of claim 18 , wherein the number of the plurality of processor cores is approximately 128.

20. The method of claim 18 , wherein the size of each of the plurality of caches is 16 kilobytes.

21. The method of claim 18 , wherein the size of each of the plurality of memories is 256 kilobytes.

22. A multi-core computer processor comprising:
a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture;
a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores; and
a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, and wherein each of the plurality of processor cores has a one-to-one relationship with a different locality-encoded, non-virtualized address range to a corresponding logical partition,
wherein at least one of a number of the plurality of processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is selected to optimize a reverse-time-migration (RTM) computation, and wherein the number of cores is selected to saturate the off-chip memory bandwidth.

Assignees

• Univ California
• Fraunhofer Ges Forschung

Inventors

• Shalf John
• Donofrio David
• Oliker Leonid
• Kruger Jens
• Williams Samuel

Classifications

• Y02D10/12

  Cross-Sectional Technologies · mapped topic

• Y02D10/13

  Cross-Sectional Technologies · mapped topic

• G06F15/7825 Primary

  Globally asynchronous, locally synchronous, e.g. network on chip · CPC title

• G06F12/0842 Primary

  for multiprocessing or multitasking · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title