Signal transfer device that maintains order of a read request and write request in posted write memory access

Patent metadata

Field	Value
Publication number	US-10078470-B2
Application number	US-201615056916-A
Country	US
Kind code	B2
Filing date	Feb 29, 2016
Priority date	Mar 19, 2015
Publication date	Sep 18, 2018
Grant date	Sep 18, 2018

Abstract

A signal transfer device includes an interface and a read and write circuit. The interface has a posted write data protocol and transfers data to a memory control device that controls access to a shared memory. If a write request for writing data to the shared memory via the interface is issued, the read and write circuit acquires a write address from the write request, and puts a read request for reading data from the write address on standby until a transfer amount of write data exceeds a total size of buffers on a signal transfer path to the shared memory.

First claim

What is claimed is:

1. A signal transfer device comprising:
an interface to transfer data from the signal transfer device to a shared memory via a memory control device that controls access to the shared memory, wherein the interface operates with a posted write data protocol, wherein the memory control device is operable to change an order of read and write requests received from the signal transfer device, and wherein a data path that traverses from the signal transfer device and through the memory control device includes buffers to temporarily store the read and write requests issued to the shared memory; and
a read and write circuit to store a total size of the buffers on the data path, to detect a write request issued by the signal transfer device to a write address in the shared memory, to detect a read request from the signal transfer device for the write address in the shared memory, to put the read request on standby in the signal transfer device in response to detecting that the read request and the write request are both intended for the write address, and to release the read request from the standby to issue the read request from the signal transfer device to the write address in the shared memory in response to determining that an amount of write data issued from the signal transfer device to the shared memory exceeds the total size of the buffers on the data path.

2. The signal transfer device of claim 1 , wherein the read and write circuit measures a transfer interval of the write request, determines if the transfer interval of the write request exceeds a predetermined time, and issues a dummy write instruction based on a determination that the transfer interval of the write request exceeds the predetermined time.

3. The signal transfer device of claim 2 , wherein the read and write circuit includes a write address first-in, first-out memory to store, in a first-in, first-out fashion, the write address acquired from the write request and a validity flag for the write address indicating that data is being written to the shared memory, and
wherein the read and write circuit further determines if the validity flag for the write address stored in the write address first-in, first-out memory is valid, and issues the dummy write instruction based on a determination that the validity flag for the write address stored in the write address first-in, first-out memory is valid.

4. The signal transfer device of claim 2 , wherein the read and write circuit further determines if the read request is put on standby, and issues the dummy write instruction based on a determination that the read request is put on standby.

5. The signal transfer device of claim 3 , wherein the read and write circuit further determines if the write address first-in, first-out memory is filled with the write address, and issues the dummy write instruction based on a determination that the write address first-in, first-out memory is filled with the write address.

6. An information processing apparatus comprising:
a memory control device to control access to a shared memory; and
the signal transfer device of claim 1 .

7. A signal transfer method comprising:
transferring data from a signal transfer device to a memory control device via an interface having a posted write data protocol, the memory control device controlling access to a shared memory and operable to change an order of read and write requests received from the signal transfer device, wherein a data path that traverses from the signal transfer device and through the memory control device includes buffers to temporarily store the read and write requests issued to the shared memory;
storing a total size of the buffers on the data path;
issuing, with the signal transfer device, a write request for writing data to a write address in the shared memory;
detecting, from the signal transfer device, a read request for reading data from the write address in the shared memory;
putting the read request on standby in the signal transfer device in response to detecting that the read request and the write request are both intended for the write address; and
releasing the read request from the standby to issue the read request from the signal transfer device to the write address in the shared memory in response to determining that an amount of write data issued by the signal transfer device to the shared memory exceeds the total size of the buffers on the data path.

8. The signal transfer method of claim 7 , further comprising:
measuring a transfer interval of the write request;
determining if the transfer interval of the write request exceeds a predetermined time; and
issuing a dummy write instruction based on a determination that the transfer interval of the write request exceeds the predetermined time.

9. The signal transfer method of claim 8 , further comprising:
storing the write address and a validity flag for the write address in a write address first-in, first-out memory in a first-in, first-out fashion, the validity flag indicating that data is being written to the shared memory;
determining if the validity flag for the write address stored in the write address first-in, first-out memory is valid; and
issuing the dummy write instruction based on a determination that the validity flag for the write address stored in the write address first-in, first-out memory is valid.

10. The signal transfer method of claim 8 , further comprising:
determining if the read request is put on standby; and
issuing the dummy write instruction based on a determination that the read request is put on standby.

11. The signal transfer method of claim 9 , further comprising:
determining if the write address first-in, first-out memory is filled with the write address; and
issuing the dummy write instruction based on a determination that the write address first-in, first-out memory is filled with the stored write address.

12. A non-transitory recording medium storing a program for causing a computer to execute a signal transfer method comprising:
transferring data from a signal transfer device to a memory control device via an interface having a posted write data protocol, the memory control device controlling access to a shared memory and operable to change an order of read and write requests received from the signal transfer device due, wherein a data path that traverses from the signal transfer device and through the memory control device includes buffers to temporarily store the read and write requests issued to the shared memory;
storing a total size of the buffers on the data path;
issuing, with the signal transfer device, a write request for writing data to a write address in the shared memory;
detecting, from the signal transfer device, a read request for reading data from the write address in the shared memory;
putting the read request on standby in the signal transfer device in response to detecting that the read request and the write request are both intended for the write address; and
releasing the read request from the standby to issue the read request from the signal transfer device to the write address in the shared memory in response to determining that an amount of write data issued by the signal transfer device to the shared memory exceeds the total size of the buffers on the data path.

Assignees

• Suzuki Masahiro
• Ricoh Co Ltd

Inventors

• Suzuki Masahiro

Classifications

• G06F13/1668 Primary

  Details of memory controller · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0629

  Configuration or reconfiguration of storage systems · CPC title