Adaptive nonlinear system control using robust and low-complexity coefficient estimation

Patent metadata

Field	Value
Publication number	US-10075201-B1
Application number	US-201715648205-A
Country	US
Kind code	B1
Filing date	Jul 12, 2017
Priority date	Jul 12, 2017
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

An adaptive controller for a nonlinear system includes a Volterra filter having a transfer function defined by P coefficients. The controller includes an alignment/compensation circuit, which aligns the input samples to the output samples of the nonlinear system. The controller generates a P×P matrix using at least one of input samples to, or output samples from the nonlinear system and normalizes each element of the P×P matrix using a respective normalization factor. The controller generates and solves a system of P linear equations from the P×P matrix and a P×1 matrix derived from input and output samples of the nonlinear system using Cholesky decomposition that may include Fast Inverse Square Root operations and forward backward elimination to generate P values. The controller multiplies each of the P values by an inverse of a respective one of the normalization factors to generate the P coefficients for the Volterra filter.

First claim

The invention claimed is:

1. An adaptive controller for a nonlinear system, the controller comprising:
a non-linear signal processing circuit;
a circuit based on a Volterra series, coupled to receive input sample values and provide output signals as an input terminal of the non-linear signal processing circuit, the circuit based on the Volterra series having a transfer function defined by a predetermined number, P, of coefficients;
an alignment and compensation circuit, coupled to the input terminal and to an output terminal of the nonlinear signal processing circuit, the alignment and compensation circuit being arranged to align the input samples and output samples of the nonlinear signal processing circuit; and
a processor, configured to:
generate a P×P matrix using samples from the nonlinear signal processing circuit;
normalize elements in the P×P matrix using respective normalization factors;
solve a system of P linear equations based on the P×P matrix to obtain P values;
multiply ones of the P values by inverses of respective ones of the normalization factors to generate the P coefficients; and
apply the P coefficients to the circuitry based on the Volterra series to compensate signals processed by the nonlinear signal processing circuit.

2. The adaptive controller of claim 1 , wherein the processor is configured to:
receive output sample values of an analog output signal of the nonlinear signal processing circuit;
apply a Volterra series to the output sample values of the nonlinear signal processing circuit to generate multiple values;
generate the P×P matrix from the multiple values; and
calculate the normalization factors based on P diagonal elements of the P×P matrix.

3. The adaptive controller of claim 2 , wherein the multiple values include M rows of values, where M is an integer greater than P and less than 20000, and the processor is configured to normalize each element of the P×P matrix by:
calculating

σ
i

=

M

a
ii

using a Fast Inverse Square Root operation for each of the P diagonal elements, a ii , of the P×P matrix; and
multiplying each element, a ij , of the P×P matrix by σ i ·σ j , where i, jϵ{1, 2, . . . , P}.

4. The adaptive controller of claim 1 , wherein the nonlinear signal processing circuit is a power amplifier of a communication equipment, the circuitry based on the Volterra series includes a digital postdistortion filter, and the processor is configured to:
generate the P×P matrix by applying output samples of the power amplifier to the Volterra series;
decompose the P×P matrix into a lower triangular matrix, a diagonal matrix, and an upper triangular matrix corresponding to a complex conjugate of the lower triangular matrix to generate the system of P linear equations; and
apply forward-backward elimination to the P×P matrix and to a P×1 vector derived from input samples to the power amplifier solve the system of P linear equations.

5. The adaptive controller of claim 4 , wherein the processor is configured to apply Cholesky decomposition to decompose the P×P matrix.

6. The adaptive controller of claim 5 , wherein the processor is configured to apply a Fast Inverse Square Root operation to the elements of the diagonal matrix as a part of the Cholesky decomposition.

7. The adaptive controller of claim 1 , wherein the normalization factors are predetermined normalization factors and the processor is configured to multiply each element of the P×P matrix by a respective one of the predetermined normalization factors.

8. The adaptive controller of claim 1 , wherein the nonlinear system is a power amplifier of communication equipment and the circuitry based on the Volterra series includes a digital predistortion filter, and the processor is configured to:
generate the P×P matrix by applying input samples of the power amplifier to the Volterra series;
decompose the P×P matrix into a lower triangular matrix, a diagonal matrix, and an upper triangular matrix corresponding to a complex conjugate of the lower triangular matrix to generate a decomposed P×P matrix; and
apply forward-backward elimination to the decomposed P×P matrix and to a P×1 vector derived from input and output samples of the power amplifier to solve the system of P linear equations.

9. The adaptive controller of claim 8 , wherein the processor is configured to apply Cholesky decomposition to decompose the P×P matrix.

10. The adaptive controller of claim 1 , wherein the processor includes a single-precision floating-point digital signal processor (DSP).

11. A method for generating a digitally predistorted signal for a power amplifier of a communication device, the method comprising:
applying input samples to be modified to a digital predistortion (DPD) filter corresponding to a Volterra series and having a predetermined number, P, of coefficients, to generate predistorted samples;
converting the predistorted samples to an analog signal to be applied to an input terminal of the power amplifier;
digitizing an output signal provided by the power amplifier to produce output samples;
building a system of P linear equations, defined by a P×P matrix based on the input samples or the output samples;
normalizing elements of the P×P matrix using respective normalization factors;
solving the system of P linear equations based on the P×P matrix to generate P values;
multiplying ones of the P values by inverses of respective ones of the normalization factors to generate the P coefficients for the DPD filter; and
applying the P coefficients to the DPD filter.

12. The method of claim 11 , further comprising generating the normalization factors from diagonal elements of the P×P matrix.

13. The method of claim 11 , further comprising:
building the P×P matrix including:
receiving the output samples of the power amplifier;
applying the output samples to the Volterra series to generate multiple rows of values; and
generating the P×P matrix from the multiple rows of values;

wherein building the system of P linear equations includes generating a P×1 vector from the input and output samples of the power amplifier.

14. The method of claim 13 , wherein solving the system of P linear equations further includes decomposing the P×P matrix using Cholesky decomposition and applying forward and backward elimination to the system of P linear equations including the decomposed P×P matrix and the P×1 vector.

15. The method of claim 11 , further comprising
building the P×P matrix including:
receiving the input samples to the DPD filter;
applying the input samples to the Volterra series to generate multiple rows of values; and
generating the P×P matrix from the multiple rows of values;

wherein building the system of P linear equations includes generating a P×1 vector derived from the input and output samples of the power amplifier.

16. The method of claim 15 , wherein solving the system of P linear equations includes decomposing the P×P matrix using Cholesky decomposition and applying forward and backward elimination to the system of linear equations including the decomposed P×P matrix and the P×1 vector.

17. The method of claim 11 , wherein the normalization factors are predetermined normalization factors and normalizing

Assignees

• Intel Ip Corp

Inventors

• Gazneli Avi
• Kerner Michael
• Almog Itay
• Knoll Amit

Classifications

• H03F1/3247

  using feedback acting on predistortion circuits (H03F1/3264 takes precedence) · CPC title

• H03F3/245

  with semiconductor devices only · CPC title

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H03F2200/294

  the amplifier being a low noise amplifier [LNA] · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title