Methods and apparatus for controlling multiple-input and multiple-output operation in a communication device based on a position sensor input
US-9628136-B2 · Apr 18, 2017 · US
US10075199B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10075199-B2 |
| Application number | US-201715652234-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jul 17, 2017 |
| Priority date | Jul 17, 2016 |
| Publication date | Sep 11, 2018 |
| Grant date | Sep 11, 2018 |
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Disclosed herein are front-end architectures for wireless communication that support a wide range of combinations of uplink carrier aggregation (UL CA) and simultaneous multiple-input multiple-output (MIMO) functionality. Embodiments can include a separate mid-band power amplifier module and a separate high band power amplifier module, and can establish various numbers of antenna outputs from these modules to connect to available diplexers or triplexers in selected ways to cover all intended use cases. Duplication of filters, duplexers, and/or quadplexers is reduced or minimized by re-using filtering in a selectively designed MIMO receive module that supports switch-combined TX filters. A UL CA power amplifier module makes use of the MIMO receive module, as well as the re-use of available filters in the mid-band primary power amplifier module.
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What is claimed is: 1. A front-end architecture for wireless communication comprising: a plurality of diplexers coupled to an antenna switch module having a first throw configured to be coupled to a first antenna and a second throw configured to be coupled to a second antenna; a first module having a low-band power amplifier with integrated duplexer, the first module coupled to the antenna switch module bypassing the plurality of diplexers; a second module having a mid-band power amplifier with integrated duplexer, a first output coupled to the antenna switch module bypassing the plurality of diplexers, a second output coupled to a first diplexer of the plurality of diplexers, and a third output coupled to a second diplexer of the plurality of diplexers; a third module having a high-band power amplifier with integrated duplexer, a first output coupled to the antenna switch module bypassing the plurality of diplexers, a second output coupled to a third diplexer of the plurality of diplexers, and a third output coupled to a fourth diplexer of the plurality of diplexers; a fourth module having a plurality of filters that includes a mid-band receive filter, a high-band receive filter, and a transmit filter, the fourth module including a first output coupled to the first diplexer, a second output coupled to the second diplexer, a third output coupled to the third diplexer, and a fourth output coupled to the fourth diplexer; and a fifth module having a power amplifier configured for uplink carrier aggregation, the fifth module configured to selectively couple to the fourth module, to the third module, and to the second module to utilize filters within the modules in one or more uplink carrier aggregation operating modes. 2. The front-end architecture of claim 1 wherein the first diplexer, the second diplexer, the third diplexer, and the fourth diplexer each includes a high-pass filter configured to pass high-band signals and a mid-band bandpass filter configured to pass mid-band signals. 3. The front-end architecture of claim 1 wherein the front-end architecture is configured to provide uplink carrier aggregation simultaneously with multiple input multiple output operation. 4. The front-end architecture of claim 3 wherein, in an operating mode that provides low-band and mid-band uplink carrier aggregation simultaneously with mid-band multiple input multiple output operation, the first module transmits low-band signals to the first port of the antenna switch module, the second module transmits and receives mid-band signals through the first diplexer, and the fourth module receives mid-band signals through the third diplexer. 5. The front-end architecture of claim 3 wherein, in an operating mode that provides low-band and mid-band uplink carrier aggregation simultaneously with high-band multiple input multiple output operation, the first module transmits low-band signals to the first port of the antenna switch module, the second module transmits mid-band signals through the first diplexer, the third module receives high-band signals through the third diplexer, and the fourth module receives high-band signals through the first diplexer. 6. The front-end architecture of claim 3 wherein, in an operating mode that provides low-band and high-band uplink carrier aggregation simultaneously with mid-band multiple input multiple output operation, the first module transmits low-band signals to the first port of the antenna switch module, the second module receives mid-band signals through the first diplexer, the third module transmits high-band signals to the third diplexer, and the fourth module receives mid-band signals through the third diplexer. 7. The front-end architecture of claim 3 wherein, in an operating mode that provides low-band and high-band uplink carrier aggregation simultaneously with high-band multiple input multiple output operation, the first module transmits low-band signals to the first port of the antenna switch module, the third module transmits and receives high-band signals through the third diplexer, and the fourth module receives high-band signals through the first diplexer. 8. The front-end architecture of claim 3 wherein, in an operating mode that provides mid-band and mid-band uplink carrier aggregation simultaneously with mid-band multiple input multiple output operation, the second module transmits and receives mid-band signals through the first diplexer, the fifth module transmits mid-band signals to the third diplexer using the transmit filter in the fourth module, and the fourth module receives mid-band signals through the third diplexer. 9. The front-end architecture of claim 3 wherein, in an operating mode that provides mid-band and mid-band uplink carrier aggregation simultaneously with high-band multiple input multiple output operation, the second module transmits mid-band signals through the first diplexer, the fifth module transmits mid-band signals to the third diplexer using the transmit filter in the fourth module, the third module receives high-band signals through the third diplexer, and the fourth module receives high-band signals through the first diplexer. 10. The front-end architecture of claim 3 wherein, in an operating mode that provides mid-band and high-band uplink carrier aggregation simultaneously with mid-band multiple input multiple output operation, the fifth module transmits mid-band signals to the first diplexer using a filter in the second module, the third module transmits high-band signals to the third diplexer, the second module receives mid-band signals through the first diplexer, and the fourth module receives mid-band signals through the third diplexer. 11. The front-end architecture of claim 3 wherein, in an operating mode that provides mid-band and high-band uplink carrier aggregation simultaneously with high-band multiple input multiple output operation, the fifth module transmits mid-band signals to the first diplexer using a filter in the second module, the third module transmits and receives high-band signals through the third diplexer, and the fourth module receives high-band signals through the first diplexer. 12. The front-end architecture of claim 3 wherein, in an operating mode that provides high-band and high-band uplink carrier aggregation simultaneously with mid-band multiple input multiple output operation, the third module transmits and receives high-band signals through the fourth diplexer, the fifth module transmits high-band signals to the third diplexer using a filter in the third module, and the fourth module receives mid-band signals through the fourth diplexer and through the third diplexer. 13. The front-end architecture of claim 3 wherein, in an operating mode that provides high-band and high-band uplink carrier aggregation simultaneously with high-band multiple input multiple output operation, the third module transmits and receives high-band signals through the fourth diplexer and receives high-band signals through the third diplexer, the fifth module transmits high-band signals to the third diplexer using a filter in the third module, and the fourth module receives high-band signals through the fourth diplexer. 14. The front-end architecture of claim 1 further comprising a first power management unit configured to provide power to the first module and to the fifth module and a second power management unit configured to provide power to the second module and the third module. 15. A wireless device comprising: a transceiver configured to generate a plurality of transmit signals and process a plurality of received signals; a plurality of antenn
Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title
the frequencies being arranged in component carriers · CPC title
using switches for selecting the desired band (H04B1/0057 takes precedence) · CPC title
analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line (duplex arrangements H04L5/143) · CPC title
using diplexing or multiplexing filters for selecting the desired band · CPC title
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