Apparatus and method for automatic bandwidth calibration for phase locked loop

Patent metadata

Field	Value
Publication number	US-10075175-B2
Application number	US-201715464039-A
Country	US
Kind code	B2
Filing date	Mar 20, 2017
Priority date	Nov 30, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code.

First claim

We claim:

1. An apparatus comprising:
a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock;
a loop filter coupled to the TDC, wherein the loop filter is to receive a modulated output of the TDC as input, wherein the modulated output is a modulated version of the digital output code; and
a first circuitry to monitor one of: the digital output code from the TDC, an output of the loop filter, or both, to adjust bandwidth of a second circuitry having the TDC and the loop filter, wherein the first circuitry is to apply a digital code to the digital output code.

2. The apparatus of claim 1 , wherein the first circuitry is to control filter coefficients for the loop filter according to the monitored digital output code.

3. The apparatus of claim 2 , wherein the first circuitry is to control the filter coefficients for the loop filter according to the monitored digital output code and the output of the loop filter.

4. The apparatus of claim 1 comprises an oscillator coupled to the loop filter.

5. The apparatus of claim 4 comprises a divider coupled to an output of the oscillator and an input of the TDC, wherein the divider is to provide the feedback clock to the TDC.

6. The apparatus of claim 1 wherein the first circuitry is to control a resolution of the TDC according to the monitored digital output code.

7. The apparatus of claim 1 , wherein the TDC and the loop filter are part of a phase locked loop, wherein the second circuitry comprises the phase locked loop.

8. The apparatus of claim 1 , wherein the TDC and the loop filter are part of a delay locked loop wherein the second circuitry comprises the delay locked loop.

9. An apparatus comprising:
a phase locked loop including a time-to-digital converter (TDC) to receive a reference clock and a feedback clock; and
a bandwidth calibration circuitry coupled to the PLL, wherein the bandwidth calibration circuitry is to monitor one of: an output of the TDC, output of a loop filter coupled to the TDC, or both, to adjust bandwidth of the PLL;
wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; and
wherein the bandwidth calibration circuitry is to apply, at a first frequency a digital code to the digital output code.

10. The apparatus of claim 9 , wherein the bandwidth calibration circuitry is to then monitor an amplitude of the digital output code from the TDC to determine whether the amplitude is greater than a first threshold of an amplitude of the digital code applied by the bandwidth calibration circuitry.

11. The apparatus of claim 10 , wherein the bandwidth calibration circuitry is to control the TDC to cause the TDC to adjust its resolution when it is determined that the amplitude of the digital output code from the TDC is less than or equal to the first threshold of the amplitude of the digital code applied by the bandwidth calibration circuitry.

12. The apparatus of claim 10 , wherein the bandwidth calibration circuitry is to control the TDC to cause the TDC to adjust its resolution so long as the amplitude of the digital output code from the TDC is less than the first threshold of the amplitude of the digital code applied by the bandwidth calibration circuitry.

13. The apparatus of claim 10 , wherein the bandwidth calibration circuitry is to adjust coefficients of the loop filter to when it is determined that the amplitude of the digital output code from the TDC is less than or equal to the first threshold of the amplitude of the digital code applied by the bandwidth calibration circuitry.

14. The apparatus of claim 10 , wherein the bandwidth calibration circuitry is to adjust coefficients of the loop filter so long as the amplitude of the digital output code from the TDC is less than the first threshold of the amplitude of the digital code applied by the bandwidth calibration circuitry.

15. The apparatus of claim 10 , wherein the bandwidth calibration circuitry is to apply, at the second frequency the digital code, wherein the second frequency is higher than the first frequency.

16. The apparatus of claim 15 , wherein the bandwidth calibration circuitry is to then monitor an amplitude of the digital output code from the TDC to determine whether the amplitude is greater than a second threshold of an amplitude of the digital code applied by the bandwidth calibration circuitry.

17. The apparatus of claim 15 , wherein the bandwidth calibration circuitry is to control the TDC to cause the TDC to adjust its resolution when it is determined that the amplitude of the digital output code from the TDC is greater than or equal to the second threshold of the digital code applied by the bandwidth calibration circuitry.

18. The apparatus of claim 15 , wherein the bandwidth calibration circuitry is to control the TDC to cause the TDC to adjust its resolution so long as the amplitude of the digital output code from the TDC is greater than the second threshold of the digital code applied by the bandwidth calibration circuitry.

19. The apparatus of claim 15 , wherein the bandwidth calibration circuitry is to adjust coefficients of the loop filter to when it is determined that the amplitude of the digital output code from the TDC is greater than or equal to the second threshold of the amplitude of the digital code applied by the bandwidth calibration circuitry.

20. The apparatus of claim 15 , wherein the bandwidth calibration circuitry is to adjust coefficients of the loop filter so long as the amplitude of the digital output code from the TDC is greater than the second threshold of the amplitude of the digital code applied by the bandwidth calibration circuitry.

21. A system comprising:
a memory;
a processor coupled to the memory, the processor including a locked loop which includes:
a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; and
a loop filter coupled to the TDC, wherein the loop filter is to receive a modulated output of the TDC as input, wherein the modulated output is a modulated version of the digital output code;
a circuitry to monitor one of: the digital output code from the TDC, an output of the loop filter, or both, to adjust bandwidth of the locked loop, wherein the circuitry is to apply a digital code to the digital output code; and

a wireless interface to allow the processor to communicate with another device.

22. The system of claim 21 , wherein the locked loop is one of a phase locked loop or a delay locked loop.

Assignees

• Intel Corp

Inventors

• Park Young Min
• Elzinga Mark

Classifications

• H03M1/0607

  Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• G04F10/005 Primary

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03M1/0626 Primary

  by filtering · CPC title