Voting circuits and methods for trusted fault tolerance of a system of untrusted subsystems

Patent metadata

Field	Value
Publication number	US-10075170-B2
Application number	US-201715692024-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Sep 9, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Circuits and methods for determining a majority vote from a plurality of inputs. An example circuit includes a voting input stage, a transfer stage, and an accumulating stage. The voting input stage includes at least three input switched capacitors. The transfer stage includes transfer switched capacitors corresponding to the input switched capacitors. The transfer switched capacitors charge a voting capacitor corresponding to each input switched capacitor during a state of a clock signal. The accumulating stage includes accumulating switched capacitors connecting the voting capacitors in series. The accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during an alternate state of the clock signal. The accumulated charge of the voting capacitors represents a majority vote of the input switched capacitors.

First claim

What is claimed is:

1. A circuit comprising:
a voting input stage including at least three input switched capacitors;
a transfer stage including transfer switched capacitors corresponding to the input switched capacitors, the transfer switched capacitors charging a voting capacitor corresponding to each input switched capacitor during a state of a clock signal; and
an accumulating stage including accumulating switched capacitors connecting the voting capacitors in series, the accumulating switched capacitors causing the charges of the voting capacitors to be accumulated during an alternate state of the clock signal, the accumulated charge of the voting capacitors representing a majority vote of the input switched capacitors.

2. A circuit as in claim 1 wherein the voting input stage includes 2F+1 input switched capacitors to provide fault tolerant consensus for F faults.

3. A circuit as in claim 1 wherein the input switched capacitors are configured to be switched by binary outputs of digital circuits.

4. A circuit as in claim 1 wherein the input switched capacitors are coupled to a voltage divider to divide a circuit supply voltage among the input switched capacitors.

5. A circuit as in claim 4 wherein the voting input stage is implemented using CMOS switches connecting the voltage divider.

6. A circuit as in claim 4 wherein the voting input stage includes a resistive voltage divider at each of N input switched capacitors, each resistive voltage divider being scaled to (N−1):1.

7. A circuit as in claim 1 wherein the transfer switched capacitors are configured to charge the voting capacitors during a high state of the clock signal.

8. A circuit as in claim 1 wherein the accumulating switched capacitors cause the charges of the voting capacitors to be accumulated during a low state of the clock signal.

9. A circuit as in claim 1 wherein the accumulated charge of the voting capacitors is passed to a digital comparator.

10. A circuit as in claim 1 wherein the accumulated charge of the voting capacitors represents a high logic vote if the accumulated charge is greater than one half of the circuit supply voltage, and wherein the accumulated charge of the voting capacitors represents a low logic vote if the accumulated charge is less than one half of the circuit supply voltage.

11. A circuit as in claim 1 wherein the input switched capacitors are configured to be switched by binary outputs of a plurality of corresponding redundant digital circuits, and wherein the accumulated charge represents one digital output of the plurality of redundant digital circuits based on a majority of digital outputs of the redundant digital circuits.

12. A method comprising:
receiving at least three voting inputs, each in the form of a high or low logical bit;
converting the voting inputs to analog voltages, resulting in analog voting voltages; and
accumulating the analog voting voltages, resulting in an accumulated analog voting voltage, the accumulated analog voting voltage representing a majority vote of the voting inputs.

13. A method as in claim 12 wherein receiving at least three voting inputs includes receiving 2F+1 inputs to provide fault tolerant consensus for F faults.

14. A method as in claim 12 wherein the voting inputs correspond to binary outputs of digital circuits.

15. A method as in claim 12 wherein converting the voting inputs to analog voltages includes dividing a circuit supply voltage among the voting inputs, and for each voting input, the corresponding analog voting voltage being equal to the divided circuit supply voltage if the voting input is a high logical bit.

16. A method as in claim 12 wherein converting the voting inputs to analog voltages includes dividing a circuit supply voltage among the voting inputs, and for each voting input, the corresponding analog voting voltage being equal to a ground voltage if the voting input is a low logical bit.

17. A method as in claim 12 wherein converting the voting inputs to analog voltages includes converting the voting inputs during a high circuit clock signal.

18. A method as in claim 12 wherein accumulating the analog voting voltages includes accumulating the analog voting voltages during a low circuit clock signal.

19. A method as in claim 12 further including passing the accumulated analog voting voltage to a digital comparator.

20. A method as in claim 12 wherein the accumulated analog voting voltage represents a high logic vote if the accumulated analog voting voltage is greater than one half of the circuit supply voltage, and wherein the accumulated analog voting voltage represents a low logic vote if the accumulated analog voting voltage is less than one half of the circuit supply voltage.

21. A method as in claim 12 wherein the voting inputs correspond to binary outputs of a plurality of redundant digital circuits, and wherein the accumulated analog voting voltage represents one digital output of the plurality of redundant digital circuits based on a majority of digital outputs of the redundant digital circuits.

Assignees

• Charles Stark Draper Laboratory Inc

Inventors

• Vigeant Richard L
• De La Serna Antonio E

Classifications

• H03K19/23 Primary

  Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs · CPC title

• H03K19/0813

  Threshold logic · CPC title

• G06F21/57 Primary

  Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities · CPC title

• G06F11/08

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• H03K25/02

  comprising charge storage, e.g. capacitor without polarisation hysteresis · CPC title