Analog front end circuit of an optical pulse energy digitizer

Patent metadata

Field	Value
Publication number	US-10075154-B1
Application number	US-201615232798-A
Country	US
Kind code	B1
Filing date	Aug 9, 2016
Priority date	Aug 9, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

An analog front end circuit of an optical pulse energy digitizer includes a multiphase clock circuit, a demultiplexer configured to demultiplex a current pulse stream into demultiplexed current pulse streams, and integrate-and-dump circuits coupled with the demultiplexer. Each ingrate and dump circuit is configured to convert one of the demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream. The multiphase clock circuit includes latches having outputs coupled to a combination logic circuit. The combination logic circuit is configured to provide clock signals for the integrate-and-dump circuits.

First claim

What is claimed is:

1. An analog front end circuit of an optical pulse energy digitizer, the analog front end circuit comprising:
a demultiplexer configured to demultiplex a current pulse stream into a plurality of demultiplexed current pulse streams;
a plurality of integrate-and-dump circuits coupled to the demultiplexer, each of the plurality of the integrate-and-dump circuits being configured to convert one of the plurality of demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream; and
a multiphase clock circuit comprising a plurality of latches having outputs coupled to a combination logic circuit, the combination logic circuit being configured to provide a plurality of clock signals for the plurality of integrate-and-dump circuits, wherein each of the clock signals is a respective clock signal for a respective integrate-and-dump circuit of the integrate-and-dump circuits.

2. The analog front end circuit of claim 1 , further comprising:
a plurality of sample and hold circuits coupled with the plurality of integrate-and-dump circuits and configured to sample and hold the demultiplexed voltage pulse stream produced by the integrate-and-dump circuits, wherein each of the sample and hold circuits is a respective sample and hold circuit for a respective integrate-and-dump circuit of the integrate-and-dump circuits.

3. The analog front end circuit of claim 1 , further comprising:
a plurality of amplifiers coupled with the plurality of integrate-and-dump circuits, wherein each of the plurality of the amplifiers is a respective amplifier for a respective integrate-and-dump circuit of the integrate-and-dump circuits.

4. The analog front end circuit of claim 1 , wherein the demultiplexer is a 1:N demultiplexer configured to lower a repetition rate of each particular demultiplexed current pulse stream of the plurality of demultiplexed current pulse streams N-times in comparison to a repetition rate of the current pulse stream generated by a photodiode.

5. The analog front end circuit of claim 1 , wherein the latches of the multiphase clock circuit comprises a set of odd latches having a clock input coupled to receive a master clock signal and a set of even latches having a clock input coupled to receive an inverted master clock signal.

6. The analog front end circuit of claim 1 , wherein the integrate-and-dump circuit is allocated a process time according to the clock signals for holding a voltage and a process time for dumping the voltage according to a repetition rate of each demultiplexed current pulse stream.

7. The analog front end circuit of claim 1 , the multiphase clock circuit comprises differential signal lines and the differential signal lines are crossed at a location between a last latch and a first latch of the latches to achieve an inversion operation.

8. The analog front end circuit of claim 1 , wherein the multiphase clock circuit comprises an inverter or a NAND gate between a last latch and a first latch of the latches.

9. A method of conditioning signals in an analog front end circuit of an optical pulse energy digitizer, the method comprising:
demultiplexing a current mode pulse stream into N demultiplexed current mode pulse streams using a demultiplexer, where N is an integer; and
converting each of the demultiplexed current mode pulse streams to each of a plurality of respective voltage mode pulse streams using a set of N integrate-and-dump circuits, wherein the demultiplexer and the set of the integrate-and-dump circuits are clocked by N clock signals, the N clock signals being provided by a multiphase clock circuit comprising a set of N latches having N outputs coupled to a combination logic circuit, the combination logic circuit being configured to provide the N clock signals.

10. The method of claim 9 , further comprising:
receiving a master clock signal at the multiphase clock circuit.

11. The method of claim 10 , wherein the master clock signal is synchronized with an optical pulse stream associated with the current mode pulse stream.

12. The method of claim 11 , further comprising converting the optical pulse stream to the current mode pulse stream.

13. The method of claim 9 , wherein the demultiplexer is a 1:N demultiplexer.

14. The method of claim 9 , wherein the N latches are arranged serially such that an output of a preceding latch is coupled to an input of a succeeding latch, wherein an output of a last latch in the set of the latches is coupled an input of an inverter and an output of the inverter is coupled to an input of an initial latch in the set of the N latches.

Assignees

• Rockwell Collins Inc

Inventors

• Hsieh Han Chi

Classifications

• H03K17/007

  with several outputs only · CPC title

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K5/15066 Primary

  using bistable devices (H03K5/15093 takes precedence) · CPC title