High power W-band/F-band Schottky diode based frequency multipliers

Patent metadata

Field	Value
Publication number	US-10075151-B2
Application number	US-201514952361-A
Country	US
Kind code	B2
Filing date	Nov 25, 2015
Priority date	Aug 25, 2011
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A solid state device chip including diodes (generating a higher frequency output through frequency multiplication of the input frequency) and a novel on-chip power combining design. Together with the on-chip power combining, the chip has increased efficiency because the diodes' anodes, being micro-fabricated simultaneously on the same patch of a GaAs wafer under identical conditions, are very well balanced. The diodes' GaAs heterostructure and the overall chip geometry are designed to be optimized for high power operation. As a result of all these features, the device can generate record-setting power having a signal frequency in the F-band and W-band (30% conversion efficiency).

First claim

What is claimed is:

1. A Schottky diode based all-solid-state frequency multiplier, comprising:
a substrate; and
a single chip mounted on the substrate, the single chip configured for outputting an output power of at least 100 milliwatts (mW) at a frequency of at least 70 GHz in response to input power having an input frequency, including components for handling the input power of at least 200 mW and a plurality of on-chip power combined multiplying structures, each multiplying structure comprising:
an input antenna or input E-probe,
a plurality of Schottky diodes,
an output antenna or output E-probe,
a first impedance matching structure connected to the Schottky diodes and the output antenna or the output E-probe, and
a second impedance matching structure connected to the Schottky diodes and the input antenna or the input E-probe, and

wherein:
the input power received from a transmission line is distributed to each of the multiplying structures using the input antennas or the input E-probes located on the chip, each of the input antennas or the input E-probes connected to a different one of the multiplying structures, and
the Schottky diodes each have their anode size and epi-structure configured to generate a higher frequency output through frequency-multiplication of the input frequency so that each of the higher frequency outputs can be combined to form the output power of at least 100 mW using the multiple output E-probes or output antennas of the different multiplying structures.

2. The multiplier of claim 1 , wherein:
the multiplier further comprises a waveguide combining structure connected to the output E-probes or output antennas, and
the epi-structure and the chip's geometry are optimized,
such that the output power is higher than 100 milliwatts.

3. The multiplier of claim 1 , wherein the epi-structure comprising a GaAs heterostructure and the chip's geometry are such that each of the diodes can handle 80 milliwatts of the input power.

4. The multiplier of claim 3 , wherein the output power has a frequency in an F-band and/or W-band.

5. A multiplier device, comprising:
a waveguide block comprising an input waveguide, wherein the input waveguide guides an input signal having a frequency and an input power; and
a chip connected to the input waveguide, the chip comprising two or more multiplying structures, wherein:
each of the multiplying structures include:
an input E-probe structured for receiving the input signal from the input waveguide,
two or more Schottky diodes,
one or more stripline based input matching networks structured to transmit the input signal from the input E-probe to the two or more Schottky diodes, to generate output power comprising an output signal having two or three times the frequency of the input signal using the nonlinear properties of the Schottky diodes,
one or more stripline based output matching networks structured for transmitting the output signal from each of the Schottky diodes to an output E-probe,
the output E-probe structured for transmitting a multiplier output, comprising a sum of the output powers generated in each of the Schottky diodes, off the single chip and into an output waveguide, and so that a combination of the output powers is a combined output power of at least 100 milliwatts (mW) at a frequency of at least 70 GHz in response to the input signal having the input power of at least 200 milliwatts.

6. The device of claim 5 , wherein the waveguide block comprises metal.

7. The device of claim 5 , wherein:
each of the multiplying structures include metal direct current (DC) bias lines for biasing the Schottky diodes to optimize the device performance, and
a total thickness of the chip including the metal DC bias lines and a substrate for the chip is in a range of 3 micrometers-100 micrometers.

8. The device of claim 5 , wherein:
each of the multiplying structures include metal direct current (DC) bias lines for biasing the Schottky diodes to optimize the device performance, and
a total thickness of the chip including the metal DC bias lines and the substrate for the chip is at least 3 micrometers.

9. The device of claim 5 , wherein the input signal is received from a source outputting the frequency of at least 23 Gigahertz (GHz).

10. The device of claim 9 , wherein the output signal has an output frequency in a W-band and/or F band of frequencies.

11. The device of claim 5 , wherein:
the input E-probes include more than one input E-probe within the input waveguide,
a top surface of the chip is perpendicular or parallel to a longitudinal axis of the input waveguide and perpendicular to the longitudinal axes of the output waveguides,
and
half of the output E-probes extend from opposite sides of the chip with regards to the other half of the output E-probes.

12. The device of claim 11 , further comprising:
output waveguides including a first waveguide and a second waveguide on the opposite sides of the chip to receive the multiplier outputs, and
a waveguide combiner combining the first waveguide and the second waveguide.

13. A method of fabricating a solid-state device, comprising:
micro-fabricating a chip including diodes, on-chip power combining, and on-chip power distribution, wherein:
the on-chip power distribution distributes an input power, transmitted onto the chip and having an input frequency, among the diodes,
the diodes each comprise an anode and a Schottky diode heterostructure,
the diodes each generate a higher frequency output through frequency multiplication of the input frequency,
each of the higher frequency outputs are combined to form a combined output power using the on-chip power combining,
the anodes are micro-fabricated simultaneously on a same patch of a semiconductor wafer and under identical conditions, and
the anodes are balanced in terms of electrical behavior; and

such that the device when biased generates the combined output power of at least 100 milliwatts (mW) at a frequency of at least 70 GHz in response to input power having an input power of at least 200 milliwatts.

14. The method of claim 13 , further comprising selecting the Schottky diode heterostructure and the chip's geometry such that the chip outputs the combined output power generated by each multiplying structure operating at a frequency in an F-band and/or W-band of frequencies.

15. The method of claim 13 , comprising:
fabricating the chip comprising two or more multiplying structures, wherein:
each of the multiplying structures include:
the on-chip distribution including an input E-probe structured for receiving an input signal, having the input frequency, from an input waveguide,
the diodes comprising two or more Schottky diodes,
the on-chip distribution including one or more stripline-based input matching networks structured to transmit the input signal, from the input E-probe to the two or more Schottky diodes, to generate output power having an output signal two or three times the input frequency of the input signal using nonlinear properties of the Schottky diodes,
the on-chip power combining including one or more stripline-based output matching networks structured for transmitting the output signal from each of the Schottky diodes to an output E-probe, and
the output E-probe structured for transmitting a multiplier output, comprising a sum of the output powers of the output signal generated in each of the Schottky diodes, off the single chip and into an output waveguide.

16. The method of claim 15 , further comprising:
fabricating and/or obtaining a waveguide block, co

Assignees

• California Inst Of Techn

Inventors

• Siles Perez Jose Vicente
• Lee Choonsup
• Chattopadhyay Goutam
• Cooper Ken B
• Mehdi Imran
• Lin Robert H
• Peralta Alejandro

Classifications

• H10W44/255

  for operation at multiple different frequencies · CPC title

• H10W44/248

  for antennas · CPC title

• H10W44/234

  Arrangements for impedance matching · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W44/20

  at high-frequency [HF] or radio frequency [RF] · CPC title