Composition, laminate, method of manufacturing laminate, transistor, and method of manufacturing transistor

Patent metadata

Field	Value
Publication number	US-10074803-B2
Application number	US-201715495360-A
Country	US
Kind code	B2
Filing date	Apr 24, 2017
Priority date	Dec 12, 2012
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Laminate, method of manufacturing laminate, transistor, and method of manufacturing transistor using a composition having the following (a) to (c):
(a) a first organic compound represented by Formula (1) below (R represents a hydrogen atom or a glycidyl group. A plurality of Rs may be identical to or different from each other, but each of at least two Rs is a glycidyl group), (b) a second organic compound represented by Formula (2) below, and (c) a photocationic polymerization initiator

First claim

What is claimed is:

1. A method of manufacturing a transistor, comprising:
forming a gate electrode on a substrate;
applying a solution containing the composition comprising
(a) a first organic compound represented by Formula (1) below,
(b) a second organic compound represented by Formula (2) below, and
(c) a photocationic polymerization initiator

(R represents a hydrogen atom or a glycidyl group, a plurality of Rs may be identical to or different from each other, but each of at least two Rs is a glycidyl group),

over the gate electrode to form a coating film;
irradiating the coating film with light containing light having an absorption wavelength of the photocationic polymerization initiator contained in the coating film to form a latent image in the light-irradiated region of the coating film;
developing the coating film to form an insulator layer; and
forming a source electrode and a drain electrode on the surface of a layer including the insulator layer.

2. The method of manufacturing a transistor according to claim 1 , wherein the coating film is selectively irradiated with the light.

3. The method of manufacturing a transistor according to claim 1 , wherein at least one of the gate electrode, the source electrode, and the drain electrode is formed by:
applying a formation material containing a silane coupling agent having a group capable of capturing a metal, which is an electroless plating catalyst, to form a base film; and
capturing the metal on the surface of the base film and then performing electroless plating.

4. The method of manufacturing a transistor according to claim 3 , wherein the source electrode and the drain electrode are formed by:
forming a source base film and a drain base film, each being the base film; and
then capturing the metal on the surface of each of the source base film and the drain base film to perform electroless plating.

5. The method of manufacturing a transistor according to claim 4 , wherein the source base film and the drain base film are formed as a continuous film.

6. The method of manufacturing a transistor according to claim 3 ,
wherein the gate electrode is formed by:
forming a gate base film, which is the base film; and
then capturing the metal on the surface of the gate base film to perform electroless plating.

7. The method of manufacturing a transistor according to claim 3 , wherein the silane coupling agent has an amino group.

8. The method of manufacturing a transistor according to claim 7 , wherein the silane coupling agent is a primary amine or a secondary amine.

9. The method of manufacturing a transistor according to claim 3 , wherein the layer including the insulator layer includes: the insulator layer; and an organic semiconductor layer disposed on the insulator layer and having a surface on which the source electrode and the drain electrode are formed.

10. The method of manufacturing a transistor according to claim 3 , comprising:
forming the source electrode and the drain electrode; and then forming an organic semiconductor layer that is in contact with surfaces of the source electrode and the drain electrode that face each other.

11. The method of manufacturing a transistor according to claim 9 , comprising, prior to forming the source electrode and the drain electrode:
forming a resist layer having an opening corresponding to the source electrode and the drain electrode and capturing the metal on the surface of the base film formed on the surface exposed at least in the opening;
performing first electroless plating and then removing the resist layer; and
performing second electroless plating on the surface of an electrode formed by the first electroless plating to form the source electrode and the drain electrode,
wherein the energy level difference between the work function of a metal material used in the second electroless plating and the energy level of a molecular orbital used for electron transfer in a formation material of the organic semiconductor layer is smaller than the energy level difference between the work function of a metal material used in the first electroless plating and the energy level of the molecular orbital.

12. The method of manufacturing a transistor according to claim 1 , wherein the substrate is made of a non-metallic material.

13. The method of manufacturing a transistor according to claim 12 , wherein the substrate is made of a resin material.

14. The method of manufacturing a transistor according to claim 13 , wherein the substrate has flexibility.

Assignees

• Nikon Corp

Inventors

• Koizumi Shohei
• Sugizaki Takashi
• Miyamoto Kenji
• Kawakami Yusuke

Classifications

• H10P50/28

  of insulating materials · CPC title

• H10P14/683

  carbon-based polymeric organic materials, e.g. polyimides, poly cyclobutene or PVC · CPC title

• Y10T428/31511

  Of epoxy ether · CPC title

• C09D163/00

  Coating compositions based on epoxy resins; Coating compositions based on derivatives of epoxy resins · CPC title

• C09D175/14

  Polyurethanes having carbon-to-carbon unsaturated bonds · CPC title