Resistive memory and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10074692-B2
Application number	US-201815884827-A
Country	US
Kind code	B2
Filing date	Jan 31, 2018
Priority date	Dec 2, 2016
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor structure, comprising:
providing a preliminary structure, wherein the preliminary structure comprises a substrate, a plurality of transistors and a dielectric layer, the transistors are formed on the substrate, and the dielectric layer is formed on the substrate and the transistors;
forming a plurality of metal lines on the dielectric layer of the preliminary structure, wherein the metal lines comprise a plurality of first metal lines and a plurality of second metal lines disposed alternately, and the first metal lines are coupled to the transistors, respectively;
forming a plurality of barrier layers on sidewalls of the first and second metal lines, respectively; and
forming a plurality of resistance-variable layers, wherein each of the resistance-variable layers is between one of the barrier layers that is formed on one of the first metal lines and one of the barrier layers that is formed on one of the second metal lines and adjacent to the one of the barrier layers that is formed on the one of the first metal lines, and wherein forming the resistance-variable layers comprises:
forming a resistance-variable material covering the first and second metal lines and the dielectric layer of the preliminary structure; and
removing undesired portions of the resistance-variable material by a planarization process such that the first and second metal lines are exposed.

2. The method according to claim 1 , wherein the dielectric layer of the preliminary structure covers the transistors.

3. The method according to claim 1 , further comprising:
before forming the metal lines, forming a plurality of vias through the dielectric layer of the preliminary structure;
wherein the first metal lines are coupled to the transistors through the vias.

4. The method according to claim 1 , wherein forming the barrier layers comprises:
forming a barrier material conformally covering the first and second metal lines and the dielectric layer of the preliminary structure; and
removing undesired portions of the barrier material such that the first and second metal lines and portions of the dielectric layer between the first and second metal lines are exposed.

5. The method according to claim 4 , wherein the barrier material comprises at least one selected from the group consisting of: Al, Ti, Ta, Au, Ag, Pt, W, Ni, Ir, Cu, NiO x , Ta y O x , TiO x , HfO x , WO x , ZrO x , Al y O x , SrTiO x , Nb y O x and Y y O x .

6. The method according to claim 1 , wherein the resistance-variable material comprises at least one selected from the group consisting of: NiO x , Ta y O x , TiO x , HfO x , WO x , ZrO x , Al y O x , SrTiO x , Nb y O x and Y y O x .

7. The method according to claim 1 , wherein the preliminary structure has a cell region and a logic region, the first and second metal lines formed on the dielectric layer of the preliminary structure are positioned in the cell region, and the method further comprises:
before forming the barrier layers, forming a dielectric material on the preliminary structure and filling trenches between the metal lines, forming a hard mask on portions of the dielectric material and the metal lines that are in the logic region, and removing portions of the dielectric material in the cell region; and
removing the hard mask in the logic region by a planarization process used to removing undesired portions of a resistance-variable material forming the resistance-variable layers.

Assignees

• United Microelectronics Corp

Inventors

• HSU Wen-Hsin
• Chen Ko-Chi
• Chang Tzu-Yun

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H01L45/1226

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L27/2463 Primary

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic