Structure and formation method for chip package

Patent metadata

Field	Value
Publication number	US-10074637-B2
Application number	US-201715458378-A
Country	US
Kind code	B2
Filing date	Mar 14, 2017
Priority date	Oct 13, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

First claim

What is claimed is:

1. A chip package comprising:
a molding compound at least partially encapsulating a semiconductor die;
a conductive feature extending through the molding compound, the conductive feature having undulating sidewalls; and
an interfacial layer having a first surface and a second surface opposite the first surface, the first surface contacting the undulating sidewalls of the conductive feature, a first portion of the second surface being in physical contact with the molding compound, a second portion of the second surface being spaced apart from the molding compound.

2. The chip package of claim 1 , wherein the undulating sidewalls of the conductive feature have a first height variation between a highest portion and a lowest portion of respective sidewalls, and wherein the second surface of the interfacial layer has a second height variation between a highest portion and a lowest portion of the second surface.

3. The chip package of claim 2 , wherein the first height variation and the second height variation are substantially the same.

4. The chip package of claim 1 , wherein the conductive feature is a metal and the interfacial layer is an oxide of the metal.

5. The chip package of claim 4 , wherein the metal comprises copper.

6. The chip package of claim 1 , wherein the interfacial layer has undulating sidewalls at the second surface.

7. A method for forming a chip package, the method comprising:
forming a conductive feature over a carrier substrate, the conductive feature having an average grain size;
heating the conductive feature to increase the average grain size to a larger average grain size, wherein heating forms an interfacial layer on sidewalls of the conductive feature; and
forming a package layer at least partially encapsulating the conductive feature, wherein forming the package layer forms at least one gap between the package layer and the interfacial layer.

8. The method of claim 7 , wherein forming the conductive feature comprises:
depositing a seed layer on a base layer;
forming a patterned mask layer over the seed layer;
plating a metal in openings in the patterned mask layer to form the conductive feature;
removing the patterned mask layer; and
removing portions of the seed layer left exposed by removal of the patterned mask layer.

9. The method of claim 7 , wherein heating the conductive feature is performed at a temperature in a range of from about 200 degrees C. to about 400 degrees C.

10. The method of claim 7 , wherein heating the conductive feature causes the conductive feature to have an undulating surface.

11. The method of claim 7 , wherein the conductive feature is a metal and the interfacial layer is an oxide of the metal.

12. The method of claim 7 , wherein forming the package layer at least partially encapsulating the conductive feature comprises:
encapsulating the conductive feature in a molding compound.

13. The method of claim 12 , wherein encapsulating the conductive feature in a molding compound forms an undulating interface between the molding compound and the interfacial layer.

14. A packaged device comprising:
a package layer; and
an element extending through the package layer, the element comprising:
an inner region composed of a metal, and
an outer region composed of an oxide of the metal, the outer region of the element and the inner region of the element forming a first interface having an undulating shape;

wherein the package layer comprises a molding compound surrounding the element, the molding compound and the outer region of the element forming a second interface having an undulating shape, wherein the undulating shape of the first interface and the second interface have a same height variation.

15. The packaged device of claim 14 , wherein the element is a copper through via extending through the molding compound.

16. The packaged device of claim 14 , further comprising:
an integrated circuit die encapsulated in the molding compound.

17. The packaged device of claim 14 , further comprising:
a redistribution layer electrically contacting one end of the element and a connector electrically contacting another end of the element.

18. The packaged device of claim 14 , wherein the inner region of the element is a conductive material and the outer region of the element is an oxide of the conductive material.

19. The chip package of claim 6 , wherein a first height variation of the undulating sidewalls of the conductive feature is equal to a second height variation of the undulating sidewalls of the interfacial layer.

20. The method of claim 13 , wherein heating the conductive feature forms an undulating interface between the conductive feature and the interfacial layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Hung Jui-Pin
• Huang Cheng-Lin
• Liu Hsien-Wen
• Jeng Shin-Puu

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title