Storage device, controller circuit, and writing and reading method

Patent metadata

Field	Value
Publication number	US-10074398-B2
Application number	US-201715702033-A
Country	US
Kind code	B2
Filing date	Sep 12, 2017
Priority date	Jan 12, 2017
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

According to one embodiment, there is provided a storage device including a controller circuit and a storage medium. The controller circuit includes a first conversion circuit and a second conversion circuit. The first conversion circuit converts data into M-ary symbols where M is an integer of 3 or more. The second conversion circuit converts respective ones of the converted n samples of M-ary symbols into signals with L-patterned pulse width where n is an integer of 2 or more. The storage medium stores the converted n samples of signals with L-patterned pulse width. The controller circuit further includes an equalization circuit that equalizes signals read from the storage medium into the n samples of M-ary symbols.

First claim

What is claimed is:

1. A storage device comprising:
a controller circuit that includes a first conversion circuit and a second conversion circuit, the first conversion circuit converting data into M-ary symbols where M is an integer of 3 or more, the second conversion circuit converting respective ones of the converted n samples of M-ary symbols into signals with L-graded pulse width where n is an integer of 2 or more and L is an integer of M or more; and
a storage medium storing the converted n samples of signals with L-graded pulse width.

2. The storage device according to claim 1 , wherein
the controller circuit further includes an encoder that encodes data, and
the first conversion circuit converts data encoded by the encoder into M-ary symbols.

3. The storage device according to claim 1 , wherein
the second conversion circuit includes
a modulation circuit that generates first bit sequences corresponding to a number of bits capable of expressing the L-graded pulse width, in accordance with the converted n samples of M-ary symbols, and
an adjustment circuit that generates second bit sequences by changing bit orders of the first bit sequences.

4. The storage device according to claim 1 , wherein
further comprising an equalization circuit including a low-pass filter having a cutoff frequency that is lower than a frequency of signals output from the second conversion circuit and that corresponds to a frequency of M-ary symbols input to the second conversion circuit.

5. The storage device according to claim 4 , wherein
the low-pass filter downconverts a frequency of signals read from the storage medium into a frequency of M-ary symbols.

6. The storage device according to claim 1 , wherein
the second conversion circuit upconverts a bit rate of the converted n samples of M-ary symbols into a bit rate corresponding to the number of bits that can express the M-ary and performs PWM modulation so as to convert the respective ones of the converted n samples of M-ary symbols into signals of L-graded pulse width.

7. The storage device according to claim 1 , wherein
the second conversion circuit includes
a clock generation circuit configured to generate a plurality of clocks having different phase shifts relative to a reference clock from each other, and
a signal generation circuit that selects one or more clocks from the plurality of clocks in accordance with respective values of the converted n samples of M-ary symbols, and that generates the signals with L-graded pulse width by using one or more clocks selected.

8. The storage device according to claim 7 , further comprising a head configured to record information into the storage medium,
wherein the controller circuit further includes a writing signal control circuit that controls levels of the converted n samples of signals with L-graded pulse width in accordance with a pattern to be recorded by the head.

9. A controller circuit comprising:
a first conversion circuit that converts data into M-ary symbols where M is an integer of 3 or more;
a second conversion circuit that converts respective ones of the converted n samples of M-ary symbols into signals with L-graded pulse width where n is an integer of 2 or more, and that outputs the signals.

10. The controller circuit according to claim 9 , further comprising an encoder that encodes data,
wherein the first conversion circuit converts data encoded by the encoder into M-ary symbols.

11. The controller circuit according to claim 9 , wherein
the second conversion circuit includes
a modulation circuit that generates first bit sequences corresponding to a number of bits capable of expressing the L-graded pulse width in accordance with the converted n samples of M-ary symbols, and
an adjustment circuit that generates second bit sequences by changing bit orders of the first bit sequences.

12. The controller circuit according to claim 9 , wherein
further comprising an equalization circuit including a low-pass filter having a cutoff frequency that is lower than a frequency of signals output from the second conversion circuit and that corresponds to a frequency of M-ary symbols input to the second conversion circuit.

13. The controller circuit according to claim 12 , wherein
the low-pass filter downconverts the frequency of input signals into a frequency of M-ary symbols.

14. The controller circuit according to claim 9 , wherein
the second conversion circuit includes
a clock generation circuit that generates a plurality of clocks having different phase shifts relative to a reference clock from each other, and
a signal generation circuit that selects one or more clocks from the plurality of clocks in accordance with respective values of the converted n samples of M-ary symbols, and that generates the signals with L-graded pulse width by using one or more clocks selected.

15. A writing and reading method comprising:
converting data into M-ary symbols where M is an integer of 3 or more;
converting respective ones of the converted n samples of M-ary symbols into signals with L-graded pulse width where n is an integer of 2 or more; and
writing the converted n samples of signals with L-graded pulse width into a storage medium.

Assignees

• Toshiba Kk

Inventors

• Harada Kohsuke
• Yamazaki Akihiro
• Maeto Nobuhiro

Classifications

• G11B5/59622 Primary

  Gain control; Filters · CPC title

• G11B5/02

  Recording, reproducing, or erasing methods; Read, write or erase circuits therefor · CPC title

• G11B5/012

  Recording on, or reproducing or erasing from, magnetic disks (G11B17/00, G11B19/00 take precedence) · CPC title

• G11B20/1833

  by adding special lists or symbols to the coded information (G11B20/1806, G11B20/1866 take precedence) · CPC title

• G11B20/1403

  characterised by the use of two levels · CPC title