Distributed LC resonant tanks clock tree synthesis

Patent metadata

Field	Value
Publication number	US-10073937-B2
Application number	US-201614994999-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jun 29, 2011
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

A technique for implementing a clock tree distribution network having a clock buffer and a plurality of LC tanks that each take into \consideration local capacitance distributions and conductor resistances. An AC-based sizing formulation is applied to the buffer and to the LC tanks so as to reduce the total buffer area. The technique is iterative and can be fully automated while also reducing clock distribution power consumption.

First claim

What is claimed:

1. A method for automatic and iterative design of an integrated circuit by a processor, the method comprising:
receiving, at the processor, first values of LC tanks within the integrated circuit, the LC tanks comprising an electrical combination of an inductor and a capacitor;
receiving, at the processor, a layout for the integrated circuit, the layout comprising a root clock location, locations for the LC tanks, and tapered conductor lines electrically connecting the root clock location to gates within the integrated circuit;
setting, via the processor, an iso-resistance radius to zero;
iteratively modifying, via the processor, a design of the integrated circuit by repeating, until a maximum radius of the integrated circuit is reached:
increasing, via the processor, the iso-resistance radius;
inserting test LC tanks at the locations for the LC tanks within the iso-resistance radius; and
balancing the integrated circuit within the iso-resistance radius such that clock signals from the root clock location simultaneously reach end locations within the iso-resistance radius using the test LC tanks,
wherein as the maximum radius is reached, the design of the integrated circuit is finalized based on best values of modified LC tanks and a sized clock driver, to yield a finalized integrated circuit design; and

fabricating a semiconductor device using the finalized integrated circuit design.

2. The method of claim 1 , wherein the iterative modifying of the design of the integrated circuit further comprises:
recording, at each iteration, best LC tank values yet identified based on an output swing of each iteration, the best LC tank values each directly associated with a radius; and
upon the maximum radius of the integrated circuit being reached, using the best LC tank values yet identified in the finalizing of the design of the integrated circuit.

3. The method of claim 1 wherein, in addition to the iterations ending upon the maximum radius of the integrated circuit, the iterations end upon an output swing being within a threshold voltage range.

4. The method of claims 3 , wherein the threshold voltage range is equal to or less than 0.9V.

5. The method of claim 1 , wherein values of the test LC tanks are modified with each iteration.

6. The method of claim 1 , wherein a sizing of a clock driver electrically connected to the root clock location is modified up to 10% with each iteration.

7. The method of claim 1 , wherein a clock driver electrically connected to the root clock location is first sized to a specified resistance.

8. The method of claim 1 , wherein a sizing of a clock driver electrically connected to the root clock location modifies the clock driver by modifying resistance of the clock driver with each iteration.

9. The method of claim 1 , wherein the iterative modifying of the design of the integrated circuit further comprises:
modifying, via the processor, values of the test LC tanks, to yield modified LC tank values;
sizing, via the processor, a clock driver connected to the root clock location, to yield a sized clock driver; and
simulating, via the processor, the design of the integrated circuit based on the modified LC tanks and the sized clock driver, to yield an output swing.

Assignees

• Univ California

Inventors

• Guthaus Matthew

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W72/00

  Interconnections or connectors in packages · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H03K19/17728

  Reconfigurable logic blocks, e.g. lookup tables · CPC title

• H03B7/14

  active element being semiconductor device · CPC title