Virtual expansion ROM in a PCIe environment

Patent metadata

Field	Value
Publication number	US-10073805-B2
Application number	US-201514845026-A
Country	US
Kind code	B2
Filing date	Sep 3, 2015
Priority date	Sep 3, 2015
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

Methods and structure for utilizing a virtual Expansion ROM. One exemplary embodiment is a management device. The management device includes a memory, a Peripheral Component Interconnect Express (PCIe) link, and a processor. The memory stores Expansion Read-Only Memory (Expansion ROM) boot instructions for a host. The processor identifies devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link. The processor also generates a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, and provides responses describing the synthetic PCIe hierarchy to a host. Furthermore, the processor acquires PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and provides boot instructions to the host from the memory based on the PCIe read requests.

First claim

What is claimed is:

1. A management device comprising:
a memory storing Expansion Read-Only Memory (Expansion ROM) boot instructions for a host;
a Peripheral Component Interconnect Express (PCIe) link; and
a processor operable to identify devices in a PCIe hierarchy by transmitting PCIe enumeration requests via the PCIe link, to generate synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy, to provide responses describing the synthetic PCIe hierarchy to a host, to acquire PCIe read requests initiated by the host that are directed to the virtual Expansion ROM, and to provide boot instructions to the host from the memory based on the PCIe read requests
wherein the processor is further operable to mask the management device from the host by excluding the management device from the synthetic PCIe hierarchy and from a modified map describing the synthetic PCIe hierarchy thereby enabling the management device to engage in sideband management of the PCIe hierarchy without the knowledge of host.

2. The management device of claim 1 , wherein:
the memory stores one set of boot instructions for Complex Instruction Set Computing (CISC) processors, and another set of boot instructions for Reduced Instruction Set Computing (RISC) processors, and
the processor is further operable to select a set of boot instructions to transmit to the host, based on whether the host utilizes a CISC processor or a RISC processor.

3. The management device of claim 1 , wherein:
the host comprises a Single Root Input/Output Virtualization (SR-IOV) host, and the memory stores multiple sets of boot instructions that each correspond with a different Virtual Function (VF).

4. The management device of claim 1 , wherein:
the processor is operable to maintain configuration space data, in the memory, for the devices in the PCIe hierarchy, and to acquire and process requests initiated by the host that are directed to configuration space.

5. The management device of claim 1 , wherein:
the processor is further operable to generate a modified map of the PCIe hierarchy by adding the virtual Expansion ROM to a device on the PCIe hierarchy.

6. The management device of claim 1 , wherein:
the processor is further operable to generate a modified map of the PCIe hierarchy by adding a virtual device, comprising the virtual Expansion ROM, to the PCIe hierarchy.

7. A method comprising:
identifying devices in a PCIe hierarchy by transmitting PCIe enumeration requests via a PCIe link of a management device;
generating a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy;
providing responses describing the synthetic PCIe hierarchy to a host;
enabling the management device to engage in sideband management of the PCIe hierarchy without the knowledge of the host;
acquiring PCIe read requests initiated by the host that are directed to the virtual Expansion ROM; and
transmitting boot instructions to the host from internal memory of the management device based on the PCIe read requests.

8. The method of claim 7 , wherein:
the memory stores one set of boot instructions for Complex Instruction Set Computing (CISC) processors, and another set of boot instructions for Reduced Instruction Set Computing (RISC) processors, and
the method further comprises selecting a set of boot instructions to transmit to the host, based on whether the host utilizes a CISC processor or a RISC processor.

9. The method of claim 7 , wherein:
the host comprises a Single Root Input/Output Virtualization (SR-IOV) host, and the memory stores multiple sets of boot instructions that each correspond with a different Virtual Function (VF).

10. The method of claim 7 , further comprising:
maintaining configuration space data, in the memory, for each device in the PCIe hierarchy; and
acquiring and processing requests initiated by the host that are directed to configuration space.

11. The method of claim 7 , further comprising:
generating a modified map of the PCIe hierarchy by adding the virtual Expansion ROM to a device on the PCIe hierarchy.

12. The method of claim 7 , further comprising:
generating a modified map of the PCIe hierarchy by adding a virtual device, comprising the virtual Expansion ROM, to the PCIe hierarchy.

13. A non-transitory computer readable medium embodying programmed instructions which, when executed by a processor of a Peripheral Component Interconnect Express (PCIe) switch, are operable for directing the processor to:
generate a synthetic PCIe hierarchy that includes an added virtual Expansion ROM which is not present in the PCIe hierarchy;
provide responses describing the synthetic PCIe hierarchy from a management device to a host;
enable the management device to engage in sideband management of the PCIe hierarchy without the knowledge of the host;
acquire PCIe read requests initiated by the host that are directed to the virtual Expansion ROM; and
transmit boot instructions to the host from internal memory at the management device based on the PCIe read requests.

14. The medium of claim 13 , wherein:
the memory stores one set of boot instructions for Complex Instruction Set Computing (CISC) processors, and another set of boot instructions for Reduced Instruction Set Computing (RISC) processors, and
the instructions further direct the processor to select a set of boot instructions to transmit to the host, based on whether the host utilizes a CISC processor or a RISC processor.

15. The medium of claim 13 , wherein:
the host comprises a Single Root Input/Output Virtualization (SR-IOV) host, and the memory stores multiple sets of boot instructions that each correspond with a different Virtual Function (VF).

16. The medium of claim 13 , wherein the instructions further direct the processor to:
maintain configuration space data, in the memory, for each device in the PCIe hierarchy; and
acquire and process requests initiated by the host that are directed to configuration space.

17. The medium of claim 13 , wherein the instructions further direct the processor to:
generate a modified map of the PCIe hierarchy by adding the virtual Expansion ROM to a device on the PCIe hierarchy.

18. The medium of claim 13 , wherein the instructions further direct the processor to:
generate a modified map of the PCIe hierarchy by adding a virtual device, comprising the virtual Expansion ROM, to the PCIe hierarchy.

19. A system comprising:
a Peripheral Component Interconnect Express (PCIe) switch comprising:
multiple PCIe ports;
a memory storing routing instructions for devices in a PCIe hierarchy; and
a controller operable to direct the operations of switching circuitry based on the routing instructions in memory, wherein the controller is further operable to trap incoming PCIe requests from a host that are directed to an Expansion Read Only Memory (ROM); and

a management device operable to receive trapped requests from the PCIe switch via a PCIe link, the management device comprising:
a memory that stores boot instructions for the host and that is not mapped into a memory space of the PCIe hierarchy; and
a processor operable to service received trapped requests from the PCIe switch with the boot instructions, wherein the host requests multiple sets of blocks across multiple requests to fully boot, wherein the processor of the management device responds to each of the multiple requests with corresponding boot instructions from memory of the manageme

Assignees

• Avago Technologies General Ip

Inventors

• Vishwanathan Rajendran
• Subramaniyan Nagarajan
• Dodson Jeffrey Michael
• Regula Jack

Classifications

• G06F13/4282 Primary

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F13/16 Primary

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F13/105

  where the program performs an input/output emulation function · CPC title