Semiconductor device wiring pattern and connections

Patent metadata

Field	Value
Publication number	US-10070528-B2
Application number	US-201514685747-A
Country	US
Kind code	B2
Filing date	Apr 14, 2015
Priority date	Oct 15, 2012
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A semiconductor device, while being small, makes it possible to achieve low inductance responding to high speed switching. The semiconductor device includes a plurality of conductive pattern members, on each of which is mounted one or a plurality of power semiconductor chips, and a printed circuit board wherein a chip rod-form conductive connection member connected to the power semiconductor chip and a pattern rod-form conductive connection member connected to the conductive pattern member are disposed on the surface opposing the conductive pattern member. The conductive pattern member is formed of a narrow portion and a wide portion, the narrow portion of at least one conductive pattern member and the printed circuit board are connected by the pattern rod-form conductive connection member, and a current path is formed between the conductive pattern member and the power semiconductor chip connected via the chip rod-form conductive connection member to the printed circuit board.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first conductive pattern member on which is mounted a first semiconductor chip;
a second conductive pattern member on which is mounted a second semiconductor chip; and
a printed circuit board on which are formed a first wiring pattern and a second wiring pattern, wherein
the first conductive pattern member is formed of a narrow portion and a wide portion,
the first semiconductor chip is connected to the first wiring pattern via a first rod-form connection member,
the second semiconductor chip is connected to the second wiring pattern via a second rod-form connection member,
the narrow portion of the first conductive pattern member is connected to the second wiring pattern via a third rod-form connection member,
the first conductive pattern member and second semiconductor chip are electrically connected via the third rod-form connection member, second rod-form connection member, and second wiring pattern, and
a terminal connection pattern member is formed on an outer side of the narrow portion, maintaining a predetermined interval from the narrow portion, between the first conductive pattern member and the second conductive pattern member.

2. The semiconductor device according to claim 1 , wherein the first conductive pattern member and first wiring pattern are disposed opposing.

3. The semiconductor device according to claim 1 , wherein the first wiring pattern of the printed circuit board is disposed so that signs of a change rate of current flowing through the first conductive pattern member and a change rate of current flowing through the printed circuit board opposing the first conductive pattern member are positive and negative opposite signs.

4. The semiconductor device according to claim 1 , wherein the terminal connection pattern member connects to an external connection terminal.

5. The semiconductor device according to claim 1 , wherein the first conductive pattern member and second conductive pattern member are configured of a copper pattern of a thickness of 0.5 mm or more but not more than 1.5 mm.

6. The semiconductor device according to claim 4 , wherein the terminal connection pattern member is configured of a copper pattern of a thickness of 0.5 mm or more, which can hold the external connection terminal.

7. The semiconductor device according to claim 1 , wherein the first conductive pattern member and second conductive pattern member are disposed on an insulating substrate.

8. The semiconductor device according to claim 1 , wherein the first conductive pattern member and second conductive pattern member are disposed on individual insulating substrates.

9. The semiconductor device according to claim 7 , wherein a heat releasing heat transferring pattern member is formed on a side of the insulating substrate opposite to a surface on which the first conductive pattern member and second conductive pattern member are formed, and a number of heat releasing heat transferring pattern members is set to be the same as, or smaller than, a number of first conductive pattern members and second conductive pattern members.

10. The semiconductor device according to claim 1 , wherein the first wiring pattern and second wiring pattern are formed on both a front and a back surface of the printed circuit board, first wiring patterns have a same potential, and second wiring patterns have a same potential.

11. The semiconductor device according to claim 10 , wherein the first semiconductor chip and second semiconductor chip are configured of a voltage controlling semiconductor element having a main electrode,
the main electrode of the first semiconductor chip is connected to the first wiring pattern, and the main electrode of the second semiconductor chip is connected to the second wiring pattern.

12. The semiconductor device according to claim 4 , comprising a sealing member encapsulating in an interior thereof the first conductive pattern member and the printed circuit board, wherein the terminal connection pattern member includes a first pattern and a second pattern disposed maintaining a predetermined interval on the outer side of the narrow portion, the external connection terminal includes a first terminal connected to the first pattern and a second terminal connected to the second pattern, and the first terminal and second terminal are formed in positions symmetrical with respect to a central line in a width direction of the semiconductor device and protrude in a same direction from the sealing member.

13. The semiconductor device according to claim 1 , wherein
each of the first semiconductor chip and second semiconductor chip is configured of a voltage controlling semiconductor element having a gate electrode and a current detecting auxiliary electrode,
a third wiring pattern connected to the gate electrode is formed on one surface of the printed circuit board, and
a fourth wiring pattern connected to the auxiliary electrode is formed in a position on another surface of the printed circuit board opposing the third wiring pattern.

14. The semiconductor device according to claim 7 , wherein
each of the first semiconductor chip and second semiconductor chip is configured of a voltage controlling semiconductor element having a gate electrode, and
the gate electrode of the first semiconductor chip and the gate electrode of the second semiconductor chip are disposed so as to be positioned on an outer side of the insulating substrate in a longitudinal direction when a plurality of the insulating substrates are disposed.

15. The semiconductor device according to claim 8 , wherein
each of the first semiconductor chip and second semiconductor chip is configured of a voltage controlling semiconductor element having a gate electrode, and
the gate electrode of the first semiconductor chip and the gate electrode of the second semiconductor chip are disposed so as to be positioned on an outer side of the insulating substrate in a longitudinal direction when a plurality of the insulating substrates are disposed.

16. The semiconductor device according to claim 1 , wherein:
the terminal connection pattern member is formed so as to be disposed side by side with the narrow portion.

17. The semiconductor device according to claim 1 , wherein:
the terminal connection pattern member connects to an external connection terminal, and one of side edges of the terminal connection pattern member coincides with one of side edges of the wide portion.

18. A semiconductor device, comprising:
a plurality of conductive pattern members, on each of which is mounted one or a plurality of power semiconductor chips; and
a printed circuit board wherein a chip rod-form conductive connection member connected to a power semiconductor chip of the one or the plurality of power semiconductor chips and a pattern rod-form conductive connection member connected to one of the plurality of conductive pattern members are disposed on a surface opposing the plurality of conductive pattern members, wherein
a wiring pattern of the printed circuit board is disposed so that signs of a change rate of current flowing through the plurality of conductive pattern members and a change rate of current flowing through the printed circuit board opposing the plurality of conductive pattern members are positive and negative opposite signs; and wherein:
the one of the plurality of conductive pattern members is formed of a narrow portion and a wide portion, and
a terminal connection pattern member is formed on an outer side of the narrow po

Assignees

• Fuji Electric Co Ltd

Inventors

• Nakamura Hideyo
• Horio Masafumi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/016

  using moulds · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title