Flexible allocation of packet buffers

Patent metadata

Field	Value
Publication number	US-10069701-B2
Application number	US-201614994164-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jan 13, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A single memory array is coupled to the ports and configured to contain both a respective headroom allocation for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to adjustably allocate to each ingress port a respective volume of memory within the single memory array to serve as the respective headroom allocation, and to queue the data packets in the multiple queues in the single memory array for transmission through the egress ports.

First claim

The invention claimed is:

1. Communication apparatus, comprising:
multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network;
a single memory array, coupled to the ports and configured to contain both a respective headroom allocation volume size for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports; and
control logic, which is configured to:
manage for each ingress port the respective headroom allocation volume size and a respective headroom occupancy counter, and to manage a shared buffer occupancy counter,
for each packet received by any of the ingress ports, write the packet directly to the single memory array and to increment the respective headroom occupancy counter of the ingress port through which the packet was received,
for each received packet stored in the single memory array, decide whether to admit the packet to the shared buffer, and if decided to admit the packet to the shared buffer, to increment the shared buffer occupancy counter and decrement the respective headroom occupancy counter, without copying the packet from one memory location to another, and
monitor a fill level of the headroom of each ingress port based on the headroom allocation volume size and the headroom occupancy counter of the ingress port, and to apply flow-control operations for the ingress port responsively to the fill level.

2. The apparatus according to claim 1 , wherein the single memory array is configured so that the control logic can allocate any portion of the memory array to the headroom allocation of the ingress ports.

3. The apparatus according to claim 1 , wherein the control logic is configured to decrement the headroom occupancy counter of an ingress port, when a data packet is transferred from the headroom allocation of the port to an egress port.

4. The apparatus according to claim 1 , wherein the data packets received from the network are written from the ingress ports to respective locations in the single memory array, and wherein the control logic is configured to transfer the data packets directly from the respective locations to the egress ports.

5. The apparatus according to claim 4 , wherein the control logic is configured, upon writing of the data packets from the ingress ports to the respective locations in the single memory array, to place entries corresponding to the received data packets in the multiple queues for transmission through the egress ports, and to transfer the data packets from the respective headroom allocation to the shared buffer before the transmission without modifying the entries in the multiple queues.

6. A method for communication, comprising:
receiving data packets from a packet data network through an ingress port of a network element having multiple ports configured to serve as ingress ports and egress ports;
transferring the data packets from the ingress port to a single memory array, which is configured to contain both a respective headroom allocation volume size for each ingress port and a shared buffer holding the data packets for transmission in multiple queues via the egress ports;
managing for each ingress port the respective headroom allocation volume size and a respective headroom occupancy counter, and managing a shared buffer occupancy counter;
for each packet received by any of the ingress ports, writing the packet directly to the single memory array and incrementing the respective headroom occupancy counter of the ingress port through which the packet was received;
for each received packet stored in the single memory array, deciding whether to admit the packet to the shared buffer, and if decided to admit the packet to the shared buffer, incrementing the shared buffer occupancy counter and decrementing the respective headroom occupancy counter, without copying the packet from one memory location to another;
monitoring a fill level of the headroom of each ingress port based on the headroom allocation volume size and the headroom occupancy counter of the ingress port, and applying flow-control operations for the ingress port responsively to the fill level; and
queuing the data packets in the multiple queues in the single memory array for transmission through the egress ports.

7. The method according to claim 6 , further comprising configuring the single memory array so that any portion of the memory array can be allocated to the headroom allocation of the ingress ports.

8. The method according to claim 6 , comprising decrementing the headroom occupancy counter of one of the ingress ports when a data packet is transferred from the headroom allocation of the port to one of the egress ports.

9. The method according to claim 6 , wherein receiving the data packets comprises writing the data packets from the ingress ports to respective locations in the single memory array, and wherein queuing the data packets comprises transferring the data packets directly from the respective locations to the egress ports.

10. The method according to claim 9 , wherein queuing the data packets comprises, upon writing of the data packets from the ingress ports to the respective locations in the single memory array, placing entries corresponding to the received data packets in the multiple queues for transmission through the egress ports, and transferring the data packets from the respective headroom allocation to the shared buffer before the transmission without modifying the entries in the multiple queues.

11. The apparatus according to claim 1 , wherein the control logic is configured to manage for each ingress port a separate shared buffer count of data transferred from headroom allocation for the each ingress port to the shared buffer and to limit an amount of data transferred from headroom allocation for the each ingress port to the shared buffer, to a respective ingress port threshold.

Assignees

• Mellanox Tech Tlv Ltd

Inventors

• Elias George
• Gafni Barak
• Bar Tikva Shachar
• Kriss Roy
• Rubinstein Eran

Classifications

• H04L49/254

  Centralised controller, i.e. arbitration or scheduling · CPC title

• H04L43/0817 Primary

  by checking functioning · CPC title

• H04L49/108

  using shared central buffer · CPC title