Systems and methods for error detection and correction

Patent metadata

Field	Value
Publication number	US-10069596-B1
Application number	US-201615388901-A
Country	US
Kind code	B1
Filing date	Dec 22, 2016
Priority date	Dec 22, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

In an example of this disclosure, a method may include receiving, by a bit error location analyzer, a split information signal at a second data rate derived from an information signal at a first data rate. In this example, the second data rate is less than the first data rate, and the bit error location analyzer may be incapable of performing error analysis at the first data rate The method may include performing error analysis, by the bit error location analyzer, on information represented by the split information signal. In some examples, performing error analysis may include comparing the information represented by the split information signal to an information seed to determine a plurality of bit error locations in the information represented by the split information signal relative to the information seed.

First claim

What is claimed is:

1. A method comprising:
receiving, by a signal splitter, an information signal at a first data rate;
splitting, by the signal splitter, the information signal into at least a first information signal and a second information signal;
outputting, by the signal splitter, the first information signal at a second data rate less than the first data rate and the second information signal at a third data rate less than the first data rate;
receiving, by a first bit error location analyzer, the first information signal at the second data rate, wherein the first bit error location analyzer is incapable of performing error analysis at the first data rate;
performing a first error analysis, by the first bit error location analyzer, on the first information signal, wherein performing the first error analysis includes comparing the first information signal to an information seed to determine, relative to the information seed, a first plurality of bit error locations in the first information signal;
receiving, by a second bit error location analyzer, the second information signal at the third data rate, wherein the second bit error location analyzer is incapable error analysis at the first data rate;
performing a second error analysis, by the second bit error location analyzer, on the second information signal, wherein performing the second error analysis includes comparing the second information signal to the information seed to determine, relative to the information seed, a second plurality of bit error locations in the second information signal; and
generating, by a bit error location combiner, a single error location file indicating bit error locations based on a combination of the first plurality of bit error locations and the second plurality of bit error locations.

2. The method of claim 1 , further comprising performing, by one or more processors, an analysis on the single error location file for determining at least one of:
a forward error correction block size;
a respective T value for each block; or
a forward error correction symbol size.

3. The method of claim 1 , further comprising:
receiving, by a receiver, a carrier signal, which carries the information signal, from a communication channel over which the carrier signal carrying the information signal was transmitted, wherein the carrier signal is a Pulse-Amplitude Modulation-N (PAM-N) signal, where N is any positive integer;
demodulating, by the receiver, the carrier signal carrying the information signal to extract the information signal, wherein the information signal extracted from the carrier signal is a non-return-to-zero (NRZ) binary signal; and
outputting, by the receiver, the information signal extracted from the carrier signal at the first data rate to the signal splitter.

4. The method of claim 3 , further comprising:
modulating, by a transmitter, the carrier signal to carry a binary signal representative of the information seed; and
transmitting, by the transmitter, the carrier signal carrying the binary signal over the communication channel to the receiver.

5. The method of claim 1 , wherein the information seed is a binary sequence of bits that includes one or more Pseudo-Random Bit Sequence-M (PRBS-M) patterns, where M is any positive integer.

6. The method of claim 1 , further comprising:
storing, by the first bit error location analyzer, the first plurality of bit error locations in a first data structure in a memory accessible by the first bit error location analyzer; and
storing, by the second bit error location analyzer, the second plurality of bit error locations in a second data structure in a memory accessible by the second bit error location analyzer, wherein generating the single error location file indicating bit error locations based on the combination of the first plurality of bit error locations and the second plurality of bit error locations comprises generating the single error location file indicating bit error locations based on the combination of the first plurality of bit error locations stored in the first data structure and the second plurality of bit error locations stored in the second data structure.

7. The method of claim 6 , wherein the memory accessible by the first bit error location analyzer and the memory accessible by the second error location are the same.

8. The method of claim 1 , wherein the information signal is extracted from a carrier signal.

9. The method of claim 8 , wherein the carrier signal is a Pulse-Amplitude Modulation-N (PAM-N) signal, where N is any positive integer.

10. The method of claim 1 , wherein the second data rate and the third data rate are equal to the first data rate divided by a number, wherein the number is equal to a power of 2 such that:
if the number is 2, the second data rate and the third data rate are each equal to the first data rate divided by 2;
if the number is 4, the second data rate and the third data rate are each equal to the first data rate divided by 4; or
if the number is N, the second data rate and the third data rate are each equal to the first data rate divided by N.

11. The method of claim 1 , wherein the second data rate and the third data rate are the same.

12. The method of claim 1 , wherein splitting the information signal comprises splitting the information signal into at least the first information signal, the second information signal, a third information signal, and a fourth information signal, the method further comprising:
outputting the third information signal at a fourth data rate less than the first data rate and outputting the fourth information signal at a fifth data rate less than the first data rate.

13. The method of claim 12 , wherein the second data rate, the third data rate, the fourth data rate, and the fifth data rate are the same.

14. A system comprising:
a signal splitter configured to receive an information signal at a first data rate, split the information signal into at least a first information signal and a second information signal, and output the first information signal at a second data rate less than the first data rate and the second information signal at a third data rate less than the first data rate;
a first bit error location analyzer configured to receive the first information signal at the second data rate, and perform a first error analysis on the first information signal, wherein the first bit error location analyzer is configured to perform the first error analysis by comparing the first information signal to an information seed to determine, relative to the information seed, a first plurality of bit error locations in the first information signal, and wherein the first bit error location analyzer is incapable of performing error analysis at the first data rate;
a second bit error location analyzer configured to receive the second information signal at the third data rate, and perform a second error analysis on the second information signal, wherein the second bit error location analyzer is configured to perform the second error analysis by comparing the second information signal to the information seed to determine, relative to the information seed, a second plurality of bit error locations in the second information signal, and wherein the second bit error location analyzer is incapable of performing error analysis at the first data rate; and
a bit error location combiner configured to generate a single error location file indicating bit error locations based on a combination of the first plurality of bit error locations and the second plurality of bit error locations.

15. The sy

Assignees

• Juniper Networks Inc

Inventors

• Chengson David P
• Rangaswamy Granthana Kattehalli
• Ofelt David James
• Priest Edward C
• Patel Bhavesh

Classifications

• H04L27/06

  Demodulator circuits; Receiver circuits · CPC title

• H04L1/0046 Primary

  Code rate detection or code type detection (H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091) · CPC title

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H04L1/0057

  Block codes (H04L1/0061, H04L1/0064 take precedence) · CPC title

• H04L1/242

  by comparing a transmitted test signal with a locally generated replica · CPC title