High-speed MOSFET and IGBT gate driver

Patent metadata

Field	Value
Publication number	US-10069485-B2
Application number	US-201715423421-A
Country	US
Kind code	B2
Filing date	Feb 2, 2017
Priority date	Feb 2, 2017
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A gate driver integrated circuit drives an output signal onto its output terminal and onto the gate of a power transistor. In a turn-on episode, a digital input signal transitions to a digital logic high level. In response, the gate driver integrated circuit couples the output terminal to a positive supply voltage terminal, thereby driving a positive voltage onto the gate of the power transistor. In response to a high-to-low transition of the digital input signal, the driver drives a negative voltage onto the output terminal and power transistor gate for a short self-timed period of time, and then couples the output terminal to a ground terminal, thereby driving the output terminal and power transistor gate up to ground potential. The output terminal and power transistor gate are then held at ground potential in anticipation of the next turn-on episode of the power transistor.

First claim

What is claimed is:

1. A gate driver integrated circuit comprising:
an input terminal that receives a digital input signal, wherein the digital input signal has a digital logic high level during a first period of time and transitions to a digital logic low level so that the digital input signal has a digital logic low level during a second period of time, and wherein the digital input signal does not transition digital logic levels between the second period of time and a third period of time such that the digital input signal maintains the digital logic low level into and throughout the third period of time;
an output terminal;
a positive supply voltage terminal, wherein a positive supply voltage is received onto the positive supply voltage terminal, wherein the positive supply voltage is greater than any voltage of the digital input signal as received onto the input terminal;
a ground terminal;
an active pullup circuit that couples the output terminal to the positive supply voltage terminal during the first period of time;
an active pulldown circuit that drives the output terminal to a negative voltage during the second period of time in response to the digital input signal on the input terminal transitioning from the digital logic high level to the digital logic low level; and
an active grounding circuit that couples the output terminal to the ground terminal during the third period of time while the digital logic low level is still present on the input terminal, wherein the active pulldown circuit comprises a delay circuit, and wherein the delay circuit outputs a signal that determines when the active pulldown circuit stops driving the output terminal to the negative voltage and when the active grounding circuit begins coupling the output terminal to the ground terminal.

2. The gate driver integrated circuit of claim 1 , further comprising:
a first capacitor terminal; and
a second capacitor terminal, wherein the active pulldown circuit causes a capacitor coupled to the first and second capacitor terminals to be charged during the first period of time and causes the first capacitor terminal to be coupled to the ground terminal during the second period of time and causes the second capacitor terminal to be coupled to the output terminal during the second period of time.

3. The gate driver integrated circuit of claim 1 , further comprising:
a negative supply voltage terminal, wherein the active pulldown circuit couples the negative supply voltage terminal to the output terminal during the second period of time.

4. The gate driver integrated circuit of claim 1 , wherein the active pullup circuit comprises a field effect transistor, wherein a first terminal of the field effect transistor is coupled to the positive supply voltage terminal, and wherein a second terminal of the field effect transistor is coupled to the output terminal.

5. The gate driver integrated circuit of claim 1 , wherein the active pullup circuit comprises a field effect transistor through which the active pullup circuit couples the positive supply voltage terminal to the output terminal during the first period of time.

6. The gate driver integrated circuit of claim 2 , wherein the active pulldown circuit comprises a field effect transistor, wherein a first terminal of the field effect transistor is coupled to the output terminal, and wherein a second terminal of the field effect transistor is coupled to the second capacitor terminal.

7. The gate driver integrated circuit of claim 2 , wherein the active pulldown circuit comprises a field effect transistor through which the active pulldown circuit couples the second capacitor terminal to the output terminal during the second period of time.

8. The gate driver integrated circuit of claim 3 , wherein the active pulldown circuit comprises a field effect transistor through which the active pulldown circuit couples the negative supply voltage terminal to the output terminal during the second period of time.

9. The gate driver integrated circuit of claim 3 , wherein the active pulldown circuit comprises a field effect transistor, wherein a first terminal of the field effect transistor is coupled to the output terminal, and wherein a second terminal of the field effect transistor is coupled to the negative supply voltage terminal.

10. The gate driver integrated circuit of claim 1 , wherein the input terminal, the output terminal, the positive supply voltage terminal, and the ground terminal are bond pad terminals of the gate driver integrated circuit.

11. A gate driver integrated circuit comprising:
an input node onto which a digital input signal is received, wherein the digital input signal on the node has a digital logic high level during a first period of time and transitions to a digital logic low level so that the digital input signal has a digital logic low level during a second period of time, and wherein the digital input signal does not transition digital logic levels between the second period and a third period such that the digital input signal maintains the digital logic low level into and throughout the third period;
an output terminal;
an active pullup circuit that drives the output terminal to a positive voltage during the first period of time in response to the digital input signal being at the digital logic high level during the first period of time;
an active pulldown circuit that drives the output terminal to a negative voltage during the second period of time in response to the digital input signal on the input node transitioning from the digital logic high level to the digital logic low level; and
an active grounding circuit that drives the output terminal to ground potential during the third period of time while the digital logic low level is still present on the input node, wherein the gate driver integrated circuit comprises a delay circuit that causes the active pulldown circuit to stop driving the output terminal to the negative voltage and that causes the active grounding circuit to start driving the output terminal to ground potential.

12. The gate driver integrated circuit of claim 11 , wherein the input node is an input terminal of the gate driver integrated circuit.

13. The gate driver integrated circuit of claim 11 , wherein the input node is driven by an inverting logic element, and wherein an input lead of the inverting logic element is coupled to an input terminal of the gate driver integrated circuit.

14. The gate driver integrated circuit of claim 11 , wherein the active pullup circuit drives the output terminal such that a voltage on the output terminal at the end of the first period of time is a substantially stable positive voltage, wherein the active pulldown circuit drives the output terminal such that a voltage on the output terminal at the end of the second period of time is a negative voltage, and wherein the active grounding circuit drives the output terminal such that a voltage on the output terminal at the end of the third period of time is a substantially stable zero volts.

15. The gate driver integrated circuit of claim 11 , wherein the active pulldown circuit comprises a capacitor charge pump circuit.

16. The gate driver integrated circuit of claim 10 , wherein the gate driver integrated circuit is housed within a semiconductor device package, wherein the semiconductor device package has package terminals, and wherein each of the input terminal, the output terminal, the positive supply voltage terminal, and the ground terminal is coupled to a corresponding one of the package terminals of the semiconductor device package.

Assignees

• Ixys Corp
• Ixys Llc

Inventors

• Tsyrganovich Anatoliy V
• Neyman Leonid A

Classifications

• H03K19/018507 Primary

  Interface arrangements · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K17/687 Primary

  the devices being field-effect transistors · CPC title

• H03K3/012 Primary

  Modifications of generator to improve response time or to decrease power consumption · CPC title