Methods, apparatus and system for providing source-drain epitaxy layer with lateral over-growth suppression

Patent metadata

Field	Value
Publication number	US-10068978-B2
Application number	US-201715472924-A
Country	US
Kind code	B2
Filing date	Mar 29, 2017
Priority date	Mar 12, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

At least one method, apparatus and system disclosed herein for suppressing over-growth of epitaxial layer formed on fins of fin field effect transistor (finFET) to prevent shorts between fins of separate finFET devices. A set of fins of a first transistor is formed. The set of fins comprises a first outer fin, an inner fin, and a second outer fin. An oxide deposition process is performed for depositing an oxide material upon the set of fins. A first recess process is performed for removing a portion of oxide material. This leaves a portion of the oxide material remaining on the inside walls of the first and second outer fins. A spacer nitride deposition process is performed. A spacer nitride removal process is performed, leaving spacer nitride material at the outer walls of the first and second outer fins. A second recess process is performed for removing the oxide material from the inside walls of the first and second outer fins. An epitaxial layer deposition processed upon the set of fins. A portion of the lateral over-growth of epitaxial layer on the outer walls of the first and second outer fins is suppressed by the spacer nitride material.

First claim

What is claimed is:

1. A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device comprising at least one fin field effect transistor (finFET); and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system;
wherein said semiconductor device processing system is adapted to:
form a set of fins of a first transistor, said set of fins comprising a first outer fin, an inner fin, and a second outer fin;
perform an oxide deposition process for depositing an oxide material upon said set of fins and within spaces between said fins;
perform a first recess process for removing a portion of oxide material, leaving a portion of the oxide material on the inside walls of said first and second outer fins;
perform a spacer nitride deposition process for depositing a spacer nitride material upon said set of fins and on outer walls of the first and second outer fins;
perform a spacer nitride removal process, leaving spacer nitride material on a first portion of the outer walls of the first and second outer fins;
perform a second recess process for removing said oxide material from the inside walls of said first and second outer fins; and
perform an epitaxial layer deposition process upon said set of fins, wherein any lateral over-growth of epitaxial layer on said outer walls of said first and second outer fins is suppressed by said spacer nitride material at the first portion, and wherein lateral overgrowth of the epitaxial layer occurs on a second portion of the outer walls of said first and second outer fins.

2. The system of claim 1 , further comprising a design unit configured to generate a first design comprising a definition for a process mask and a definition for an operation of a FinFET device that comprises a plurality of fins, wherein data from said design unit is used by said process controller to control an operation of said semiconductor device processing system.

3. The system of claim 1 , wherein the width of said epitaxial layer is based upon said width of said fin, wherein said width of said epitaxial layer is proportional to said width of said fin.

4. The system of claim 1 , wherein said semiconductor device processing system is further adapted to perform an epitaxial layer deposition process upon a third outer fin of a second transistor adjacent to said first transistor, wherein performing an epitaxial layer deposition process upon said set of fins comprises suppressing said lateral over-growth of the epitaxial layer on said first portion such that the epitaxial layer on said first outer fin does not touch said epitaxial layer deposited on said third outer fin.

5. The system of claim 1 , wherein said semiconductor device processing system is further adapted to deposit silicon dioxide of a consistency to deposit said silicon dioxide between the inside walls of said first and second outer fins.

6. The system of claim 1 , wherein at least a portion of vertical over-growth of the epitaxial layers on said outer walls of said first and second outer fins is suppressed by said spacer nitride material.

Assignees

• Globalfoundries Inc

Inventors

• Lim Kwan-Yong
• Prindle Christopher Michael

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• H01L21/823418

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L29/0688

  Electricity · mapped topic

• H01L29/66553

  Electricity · mapped topic