Pixel circuit, driving method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-10068950-B2
Application number	US-201414775006-A
Country	US
Kind code	B2
Filing date	Oct 11, 2014
Priority date	Jul 21, 2014
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A pixel circuit, a driving method thereof and a display apparatus, the pixel circuit comprises a data voltage writing module ( 100 ), two driving modules and two light emitting modules; wherein the data voltage writing module ( 100 ) is connected with a data voltage line (Vdata), a writing control line (R) and the two driving modules, and is configured to write a first data voltage on the data voltage line (Vdata) to a first driving module ( 210 ) at first and then write a second data voltage to a second driving module ( 220 ) according to inputs from the writing control line (R); the first driving module ( 210 ) is connected with a first light emitting module ( 310 ), the second driving module ( 220 ) is connected with a second light emitting module ( 320 ); and both of the two driving modules are connected with an operating voltage line (Vdd) and a driving control line (S), and are configured to drive the corresponding light emitting module to emit light under the control of the driving control line (S). By utilizing one circuit to realize the driving of two pixels, two adjacent pixels shares several signal lines, the number of the signal lines for the pixel circuit in the display apparatus can be decreased, the cost of the integrated circuit is reduced, a pixel pitch is decreased, and a pixel density is increased.

First claim

What is claimed is:

1. A pixel circuit for driving two pixels comprising a data voltage writing module, two driving modules and two light emitting modules; wherein the data voltage writing module is connected with a data voltage line, two writing control lines and the two driving modules of the two pixels respectively, and is configured to write a first data voltage of a first pixel of the two pixels on the data voltage line to a first driving module according to input from a first writing control line among the two writing control line at first and then write a second data voltage of a second pixel of the two pixels on the data voltage line to a second driving module according to input from a second writing control line among the two writing control line in a same frame; the first driving module is connected with a first light emitting module of the first pixel, the second driving module is connected with a second light emitting module of the second pixel; and both of the two driving modules are connected with a driving control line and are configured to drive the two light emitting modules of respective pixels to emit light under the control of the driving control line, and both of the two driving modules are connected with a single operating voltage line, wherein the operating voltage line is configured to supply power to the two light emitting modules via the two driving modules.

2. The pixel circuit of claim 1 , wherein the data voltage writing module comprises a first sub-data voltage writing module and a second sub-data voltage writing module, the first sub-data voltage writing module is connected with the data voltage line, the first writing control line and the first driving module, and the second sub-data voltage writing module is connected with the data voltage line, the second writing control line and the second driving module.

3. The pixel circuit of claim 2 , wherein each of the sub-data voltage writing modules comprises a writing transistor, a gate of the writing transistor is connected with the corresponding writing control line, a source of the writing transistor is connected with the data voltage line, and a drain of the writing transistor is connected with the corresponding driving module.

4. The pixel circuit of claim 3 , wherein each of the driving modules comprises three driving transistors and a storage capacitor, wherein a source of a first driving transistor is connected with the drain of the corresponding writing transistor, a gate and a drain of the first driving transistor are connected with a gate of a second driving transistor; a drain of the second driving transistor is connected with a source of a third driving transistor, a source of the second driving transistor is connected with the data voltage line; a gate of the third driving transistor is connected with the driving control line, a drain of the third driving transistor is connected with the light emitting module; a first terminal of the storage capacitor is connected with the gate of the second driving transistor, and a second terminal of the storage capacitor is connected with the source of the second driving transistor.

5. The pixel circuit of claim 4 , wherein it further comprises a first reset transistor and a second reset transistor, a gate of the first reset transistor is connected with a reset control line, a source of the first reset transistor is connected with the first terminal of the storage capacitor in the first driving module, a drain of the first reset transistor is connected with a reset low voltage level line; a gate of the second reset transistor is connected with the reset control line, a source of the second reset transistor is connected with the first terminal of the storage capacitor in the second driving module, a drain of the second reset transistor is connected with the reset low voltage level line.

6. The pixel circuit of claim 5 , wherein the transistors are P channel thin film transistors.

7. The pixel circuit of claim 4 , wherein the transistors are P channel thin film transistors.

8. The pixel circuit of claim 3 , wherein each of the driving modules comprises four driving transistors and a storage capacitor; wherein a gate of a first driving transistor is connected with the driving control line, a source of the first driving transistor is connected with an operating voltage line, a drain of the first driving transistor is connected with a source of a second driving transistor; a gate of the second driving transistor is connected with a first terminal of the storage capacitor, a drain of the second driving transistor is connected with a source of a third driving transistor; a gate of the third driving transistor is connected with the driving control line, a drain of the third driving transistor is connected with the light emitting module; a drain of a fourth driving transistor is connected with the drain of the second driving transistor, a source of the fourth driving transistor is connected with the first terminal of the storage capacitor; a second terminal of the storage capacitor is grounded;
a gate of the fourth driving transistor in the first driving module is connected with the first writing control line, and a gate of the fourth driving transistor in the second driving module is connected with the second writing control line.

9. The pixel circuit of claim 8 , wherein it further comprises a first reset transistor and a second reset transistor, gates of both of the reset transistors are connected with a reset control line; a source of the first reset transistor is connected with the first terminal of the storage capacitor in the first driving module, a drain of the first reset transistor is connected with the second terminal of the storage capacitor in the first driving module; a source of the second reset transistor is connected with the first terminal of the storage capacitor in the second driving module, a drain of the second reset transistor is connected with the second terminal of the storage capacitor in the second driving module.

10. The pixel circuit of claim 8 , wherein the transistors are P channel thin film transistors.

11. The pixel circuit of claim 3 , wherein the transistors are P channel thin film transistors.

12. The pixel circuit of claim 3 , wherein each of the driving modules comprises four driving transistors and a storage capacitor, a gate of a first driving transistor is connected with a first driving control line, a source of the first driving transistor is connected with drains of a second driving transistor and a third driving transistor, a drain of the first driving transistor is connected with the operating voltage line; a gate of the second driving transistor is connected with a second driving control line, a source of the second driving transistor is connected with a first terminal of the storage capacitor; a gate of the third driving transistor is connected with the first terminal of the storage capacitor, a source of the third driving transistor is connected with the light emitting module; a gate and a drain of a fourth driving transistor are connected with the first terminal of the storage capacitor, a source of the fourth driving transistor is connected with the corresponding writing transistor; and a second terminal of the storage capacitor is connected with a low voltage level line.

13. The pixel circuit of claim 12 , wherein the transistors are N channel thin film transistors.

14. The pixel circuit of claim 1 , wherein the data voltage writing module comprises three writing transistors; a gate of a first writing transistor is connected with the first writing control line, a source of the first writing trans

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Optoelectronics Tech Co Ltd

Inventors

• Yang Shengji

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G06F3/042

  by opto-electronic means · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title

• G09G3/3225

  using an active matrix · CPC title