IC structure on two sides of substrate and method of forming

Patent metadata

Field	Value
Publication number	US-10068899-B2
Application number	US-201615239976-A
Country	US
Kind code	B2
Filing date	Aug 18, 2016
Priority date	Aug 18, 2016
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

First claim

What is claimed is:

1. An integrated circuit (IC) structure, comprising:
a single semiconductor substrate having a first side and an opposing, second side, wherein the single semiconductor substrate includes only a uniform semiconductor layer;
a first plurality of active devices on the first side of the single semiconductor substrate;
a second plurality of active devices on the opposing, second side of the single semiconductor substrate;
at least one through silicon via (TSV) electrically coupling at least one of the first plurality of active devices to at least one of the second plurality of active devices, wherein the at least one of the first plurality of active devices includes an n-type device, wherein the at least one of the second plurality of active devices includes a p-type device, and wherein the at least one TSV electrically couples the n-type device to the p-type device;
a first back-end-of-line (BEOL) interconnect structure electrically coupled to at least one of the second plurality of active devices on the second side of the single semiconductor substrate; and
a second BEOL interconnect structure electrically coupled to at least one of the first plurality of active devices on the first side of the single semiconductor substrate;
wherein the at least one TSV extends entirely through the single semiconductor substrate and through at least one metal layer of the first BEOL interconnect structure.

2. The IC structure of claim 1 , further comprising at least one through silicon via (TSV) electrically coupling at least one of the first plurality of active devices and the first BEOL interconnect structure to at least one of the second plurality of active devices and the second BEOL interconnect structure.

3. The IC structure of claim 1 , further comprising at least one external interconnect electrically coupling one of the first BEOL interconnect structure and the second BEOL interconnect structure to an external circuit board.

4. The IC structure of claim 1 , wherein the first plurality of active devices is less than 100 micrometers (μm) from the second plurality of active devices within the single semiconductor substrate.

5. The IC structure of claim 1 , wherein the first plurality of active devices have at least one of a different size and a different type than the second plurality of active devices.

6. The IC structure of claim 1 , wherein the TSV extends through at least one metal layer of the second BEOL interconnect structure.

7. A method, comprising:
forming a first plurality of active devices on a first side of a single semiconductor substrate, wherein a first one of the first plurality of active devices includes an n-type device, and wherein a second one of the first plurality of active devices includes a p-type device;
forming a second plurality of active devices on an opposing, second side of the single semiconductor substrate, wherein the second plurality of active devices includes a p-type device;
after forming the first plurality of active devices and the second plurality of active devices, forming a first back-end-of-line (BEOL) interconnect structure electrically coupled to at least one of the second plurality of active devices on the second side of the single semiconductor substrate;
forming a second BEOL interconnect structure electrically coupled to at least one of the first plurality of active devices on the first side of the single semiconductor substrate, wherein the single semiconductor substrate includes only a uniform semiconductor layer; and
after forming at least a portion of the first BEOL interconnect structure, forming at least one through silicon via (TSV) electrically coupling the n-type device of the first plurality of active devices to the p-type device of the second plurality of active devices;
wherein the at least one TSV extends entirely through the single semiconductor substrate and through at least one metal layer of the first BEOL interconnect structure.

8. The method of claim 7 , further comprising forming at least one through silicon via (TSV) electrically coupling at least one of the first plurality of active devices and the first BEOL interconnect structure to at least one of the second plurality of active devices and the second BEOL interconnect structure.

9. The method of claim 7 , further comprising performing an anneal to activate the first plurality of active devices and the second plurality of active devices prior to forming either of the first BEOL interconnect structure and the second BEOL interconnect structure.

10. The method of claim 7 , further comprising thinning the single semiconductor wafer prior to forming the second plurality of active devices on the opposing, second side such that the first plurality of active devices is less than 100 micrometers (μm) from the second plurality of active devices within the single semiconductor substrate after forming the second plurality of active devices.

11. The method of claim 7 , wherein the first plurality of active devices have at least one of a different size and a different type than the second plurality of active devices.

12. The method of claim 7 , wherein the forming of the at least one TSV occurs during or after the forming of the second BEOL interconnect structure.

13. An integrated circuit (IC) structure, comprising:
a single semiconductor substrate having a first side and an opposing, second side, wherein the single semiconductor substrate includes only an undoped semiconductor layer;
a first plurality of active devices in a first device layer on the first side of the single semiconductor substrate;
a second plurality of active devices in a second device layer on the opposing, second side of the single semiconductor substrate;
at least one through silicon via (TSV) electrically coupling at least one of the first plurality of active devices and at least one of the second plurality of active devices, wherein the at least one of the first plurality of active devices includes an n-type device, wherein the at least one of the second plurality of active devices includes a p-type device, and wherein the at least one TSV electrically couples the n-type device to the p-type device;
a first back-end-of-line (BEOL) interconnect structure positioned above the second device layer, wherein the first BEOL interconnect structure is electrically coupled to at least one of the second plurality of active devices on the second side of the single semiconductor substrate; and
a second BEOL interconnect structure positioned above the first device layer, wherein the second BEOL interconnect structure is electrically coupled to at least one of the first plurality of active devices on the first side of the single semiconductor substrate;
wherein the at least one TSV extends entirely through the single semiconductor substrate, the first device layer, the second device layer, at least one metal layer of the first BEOL interconnect structure and at least one metal layer of the second BEOL interconnect structure.

14. The IC structure of claim 13 , wherein the at least one TSV electrically couples the at least one of the first plurality of active devices to the at least one of the second plurality of active devices through at least one of the first BEOL interconnect structure and the second BEOL interconnect structure.

15. The IC structure of claim 13 , further comprising at least one external interconnect electrically coupling one of the first BEOL interconnect structure and the second BEOL interconnect structure to an external circuit board.

16. The IC structure of claim 13 , wherein the first pl

Assignees

• Globalfoundries Inc

Inventors

• Melville Ian D W
• Farooq Mukta G

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/00 Primary

  Package configurations · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/023

  the interconnections being through-semiconductor vias · CPC title