Shift register unit, driving circuit and method, array substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-10068658-B2
Application number	US-201514906744-A
Country	US
Kind code	B2
Filing date	Sep 16, 2015
Priority date	Apr 9, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

There are provided a shift register unit, a strobe driving circuit, a display apparatus and a driving method for the shift register unit. The shift register unit comprises: an inputting module (10) configured to control a potential of the pulling-up control node according to a signal of the first signal input terminal; a pulling-up module (20) configured to output a present stage output signal from the present stage output terminal according to a signal of the second clock signal terminal and the potential of the pulling-up control node; a pulling-down module (30) configured to pull down the potential of the pulling-up control node and the signal of the present stage output terminal to a low level according to a signal of the third clock signal terminal; a resetting module (40) configured to reset the potential of the pulling-up control node according to a signal of the second signal input terminal and pull down the signal of the present stage output terminal to a low level. Correspondingly, the pulling-down operation of the shift register unit is implemented in a simple manner, so that a number of TFTs as required, power consumption and wiring are reduced.

First claim

What is claimed is:

1. A shift register unit, comprising:
an inputting circuit connected to a first signal input terminal and a pulling-up control node, and configured to control a potential of the pulling-up control node according to a signal of the first signal input terminal;
a pulling-up circuit connected to the pulling-up control node, a second clock signal terminal and a present stage output terminal, and configured to output a present stage output signal from the present stage output terminal according to a signal of the second clock signal terminal and the potential of the pulling-up control node;
a pulling-down circuit connected to a third clock signal terminal, the pulling-up control node, the present stage output terminal and a power supply terminal, and configured to pull down the potential of the pulling-up control node and the signal of the present stage output terminal to a low level according to a signal of the third clock signal terminal; and
a resetting circuit connected to a second signal input terminal, the pulling-up control node, the present stage output terminal and the power supply terminal, and configured to reset the potential of the pulling-up control node according to a signal of the second signal input terminal and pull down the signal of the present stage output terminal to a low level; and
an isolating circuit connected to a first clock signal terminal, the second clock signal terminal, the third clock signal terminal and the pulling-up control node, and configured to reduce signal fluctuation in the shift register unit caused by signals of respective clock signal terminals, wherein
the pulling-down circuit comprises:
a third transistor, having first electrode connected to the pulling-up control node, strobe electrode connected to the third clock signal terminal, and second electrode directly connected to the power supply terminal; and
a fourth transistor, having first electrode connected to the present stage output terminal, strobe electrode connected to the third clock signal terminal, and second electrode directly connected to the power supply terminal, wherein
the isolating circuit is further connected to a first clock terminal, and comprises:
a second capacitor having a first terminal directly electrically connected to the first clock signal terminal and a second terminal directly electrically connected to the pulling-up control node; and
a fourth capacitor having a first terminal directly electrically connected to the second clock signal terminal and a second terminal directly electrically connected to the pulling-up control node.

2. The shift register unit according to claim 1 , wherein the isolating circuit is further connected to the third clock signal terminal, and comprises:
a third capacitor having a first terminal connected to the third clock signal terminal and a second terminal connected to the pulling-up control node.

3. The shift register unit according to claim 2 , wherein the signal of the first cock signal terminal, the signal of the second dock signal terminal, and the signal of the third dock signal terminal are square wave signals, and correspond to a previous stage output signal, the present stage output signal and a next stage output signal respectively, wherein the previous stage output signal is an output signal of a previous stage of shift register unit adjacent to the shift register unit, and the next stage output signal is an output signal of a next stage of shift register unit adjacent to the shift register unit.

4. The shift register unit according to claim 1 , wherein the power supply terminal is connected to the second dock signal terminal, so that the signal of the second dock signal terminal is provided to the power supply terminal to pull down the potential of the pulling-up control node and the signal of the present stage output terminal.

5. The shift register unit according to claim 1 , wherein the inputting circuit comprises:
a first transistor having first electrode and strobe electrode connected to the first signal input terminal, and second electrode connected to the pulling-up control node.

6. The shift register unit according to claim 1 , wherein the pulling-up circuit comprises: a first capacitor, having first terminal connected to the puffing-up control node; and
a second transistor, having first electrode connected to the second clock signal terminal, strobe electrode connected to a second terminal of the first capacitor, and second electrode connected to the present stage output terminal.

7. The shift register unit according to claim 1 , wherein the resetting circuit comprises: a fifth transistor, having first electrode connected to the pulling-up control node, strobe electrode connected to the second signal input terminal, and second electrode connected to the power supply terminal; and
a sixth transistor, having first electrode connected to the present stage output terminal, strobe electrode connected to the second signal input terminal, and second electrode connected to the power supply terminal.

8. The shift register unit according to claim 1 , wherein the isolating circuit is further connected to the third clock signal terminal, and comprises:
a third capacitor having a first terminal connected to the third clock signal terminal and a second terminal connected to the pulling-up control node.

9. The shift register unit according to claim 8 , wherein the signal of the first cock signal terminal, the signal of the second dock signal terminal, and the signal of the third dock signal terminal are square wave signals, and correspond to a previous stage output signal, the present stage output signal and a next stage output signal respectively, wherein the previous stage output signal is an output signal of a previous stage of shift register unit adjacent to the shift register unit, and the next stage output signal is an output signal of a next stage of shift register unit adjacent to the shift register unit.

10. A strobe driving circuit, comprising N stages of shift register units, wherein the N stages of shift register units are a first shift register unit to a N-th shift register unit, and each of the shift register units is the shift register unit according to claim 1 , where N is a natural number,
a first signal input terminal of each of a second shift register unit to the N-th shift register unit is connected to an output terminal of a previous stage of shift register unit adjacent thereto,
a second signal input terminal of each of the first shift register unit to a (N−1)-th shift register unit is connected to an output terminal of a next stage of shift register unit adjacent thereto.

11. An array substrate, comprising the strobe driving circuit according to claim 10 .

12. A display apparatus, comprising the array substrate according to claim 11 .

13. A driving method for a shift register unit, the shift register unit comprising an inputting circuit, a pulling-up circuit, a pulling-down circuit, a resetting circuit and an isolating circuit, wherein the inputting circuit is connected to a first signal input terminal and a pulling-up control node, the pulling-up circuit is connected to the pulling-up control node, a second clock signal terminal and a present stage output terminal, the pulling-down circuit is connected to a third clock signal terminal, the pulling-up control node, the present stage output terminal and a power supply terminal, the resetting circuit is connected to a second signal input terminal, the pulling-up control node, the present stage output terminal and the power supply terminal and the isolating circuit is connected to a first clock signal ter

Assignees

• Boe Technology Group Co Ltd
• Beijing Boe Display Tech Co

Inventors

• Wang Zheng

Classifications

• G09G3/3677

  suitable for active matrices only · CPC title

• G11C19/287 Primary

  Organisation of a multiplicity of shift registers · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title