Display panel and inspection method thereof

Patent metadata

Field	Value
Publication number	US-10068510-B2
Application number	US-201615373542-A
Country	US
Kind code	B2
Filing date	Dec 9, 2016
Priority date	Dec 31, 2015
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A display panel is discussed. The display panel according to an embodiment includes driver integrated circuits (ICs); data lines disposed in an active region; input pads disposed in a pad region; output pads disposed in a first inspection circuit included in the pad region, the output pads receiving first signals from the input pads; and a first switching circuit disposed in the first inspection circuit and connected to the output pads. The first switching circuit is configured to supply the first signals to the data lines. The display panel further includes first signal lines configured to supply the first signals to the output pads; a second switching circuit disposed in a second inspection circuit and connected to the data lines in the active region; and a second signal line configured to supply second signals to the second switching circuit.

First claim

What is claimed is:

1. A display panel comprising:
driver integrated circuits (ICs);
a plurality of data lines disposed in an active region;
a plurality of input pads disposed in a pad region and configured to supply a plurality of first signals to the driver ICs;
a plurality of output pads including used output pads electrically connected to first data lines among the plurality of data lines, respectively, and dummy output pads that are unused and electrically disconnected from all of the plurality of data lines, wherein the plurality of output pads are disposed in a first inspection circuit included in the pad region, the used output pads receiving the plurality of first signals from the plurality of input pads via the driver ICs;
a first switching circuit disposed in the first inspection circuit included in the pad region and connected to the used output pads, wherein the first switching circuit is configured to supply the plurality of first signals to the first data lines via the used output pads;
a plurality of first signal lines configured to supply the plurality of first signals to the used output pads via the first switching circuit;
a second switching circuit disposed in a second inspection circuit and connected to all of the plurality of data lines in the active region; and
a second signal line configured to supply a plurality of second signals to the second switching circuit,
wherein the used output pads of the first inspection circuit are grouped into a plurality of used output pad groups, and at least one dummy output pad among the dummy output pads is disposed between adjacent output pad groups among the plurality of used output pad groups, and
wherein the plurality of first signals are respectively supplied to the first data lines which are less than all of the plurality of data lines, and the second signals are supplied to all of the plurality of data lines.

2. The display panel according to claim 1 , wherein the plurality of output pads are connected to the plurality of data lines via link lines.

3. The display panel according to claim 1 , wherein the first switching circuit is positioned at a bottom side of the active region, and the second switching circuit is positioned at a left, right, or top side of the active region.

4. The display panel according to claim 1 , wherein the second signals supplied by the second switching circuit are in a direction opposite to a direction of the plurality of first signals supplied by the first switching circuit.

5. The display panel according to claim 1 , wherein predetermined output pads among the plurality of output pads are used as the dummy output pads.

6. The display panel according to claim 1 , wherein the second switching circuit receives the second signals from the second signal line and supplies the second signals to the all of the plurality of data lines.

7. The display panel according to claim 1 , wherein the plurality of first signals comprise red, green, and blue signals supplied to the plurality of first signal lines for displaying each of red, green, and blue color patterns, respectively.

8. The display panel according to claim 1 , wherein the second signals supplied to the second signal line comprise red, green, and blue signals for displaying a gray-scale pattern.

9. The display panel according to claim 1 , wherein the plurality of first signals are sequentially supplied to the plurality of data lines.

10. The display panel according to claim 1 , wherein a resistance difference between first and second output pad groups among the plurality of used output pad groups is different than a resistance difference between the second output pad group and a third output pad group among the plurality of used output pad groups.

11. The display panel according to claim 1 , further comprising:
a first pad positioned in a non-active region to connect to a first data enable circuit;
a second pad positioned in the non-active region to connect to a second data enable circuit; and
a plurality of third pads positioned in the non-active region to connect to the plurality of first signal lines, respectively.

12. The display panel according to claim 1 , wherein the plurality of first signals comprise red, green, and blue signals for displaying a first gray-scale pattern by first pixels among a plurality of pixels included in the active region and corresponding to the first data lines,
wherein the plurality of second signals comprise red, green, and blue signals for displaying a second gray-scale pattern by all of the plurality of plurality of pixels for comparing the second gray-scale pattern to the first gray-scale pattern to detect a defect.

13. The display panel according to claim 12 , wherein the first gray-scale pattern is same as the second gray-scale pattern for determining whether there is a defect in luminance in the display panel.

14. A display panel comprising:
a plurality of data lines and a plurality of gate lines disposed in an active region, the plurality of data lines crossing the plurality of gate lines to define a pixel region;
a plurality of input pads disposed in a non-active region;
a plurality of output pads including used output pads electrically connected to first data lines among the plurality of data lines, respectively, and dummy output pads that are unused and electrically disconnected from all of the plurality of data lines, wherein the used output pads are configured to receive a plurality of first signals from the plurality of input pads;
a first data enable circuit disposed in a first region and configured to supply the plurality of first signals to the first data lines via the used output pads; and
a second data enable circuit disposed in a second region and configured to supply a plurality of second signals to all of the plurality of the data lines,
wherein the plurality of first signals comprise red, green, and blue signals for displaying each of red, green, and blue color patterns, respectively,
wherein the plurality of second signals comprise red, green, and blue signals for displaying a gray-scale pattern,
wherein the used output pads are grouped into a plurality of used output pad groups, and at least one dummy output pad among the dummy output pads is disposed between adjacent output pad groups among the plurality of used output pad groups, and
wherein the plurality of first signals are respectively supplied to the first data lines which are less than all of the plurality of data lines, and the second signals are supplied to all of the plurality of data lines.

15. The display panel according to claim 14 , further comprising:
a plurality of first signal lines configured to supply the plurality of first signals to the used output pads via the first data enable circuit; and
a second signal line configured to supply the plurality of second signals to the second data enable circuit.

16. The display panel according to claim 15 , wherein the plurality of first signal lines and the plurality of second signal lines are disposed on a same layer as the plurality of gate lines to connect to the first and second data enable circuits, respectively.

17. The display panel according to claim 14 , wherein the first data enable circuit is positioned at a bottom side of the active region, and the second data enable circuit is positioned at a left, right, or top side of the active region.

18. The display panel according to claim 17 , wherein the plurality of second signals supplied by the second data enable circuit are in a direction opposite to a direction of the

Assignees

• Lg Display Co Ltd

Inventors

• Lee Junyeob

Classifications

• G09G3/006 Primary

  Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2320/0223

  Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes · CPC title

• G09G2330/12

  Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

• G09G2310/0297

  Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns · CPC title