Fault detection for a display system

US10068509B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10068509-B2
Application numberUS-201615058725-A
CountryUS
Kind codeB2
Filing dateMar 2, 2016
Priority dateMar 2, 2016
Publication dateSep 4, 2018
Grant dateSep 4, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A fault detection system is provided for a display system including an AMLCD. A video processor embeds encoded fault detection data within the digital video stream that is sent directly to the AMLCD. The fault detection data is embedded in such a manner that it is not displayed by the AMLCD. The fault detection data in the digital video stream received by the AMLCD is detected by the AMLCD and is then sent back to the video processor. The video processor compares what was sent with what is received to determine whether there is a difference which may be indicative of a fault in the AMLCD or the path of the digital video stream. As an additional check, the AMLCD may send timing error data to the video processor indicating whether the AMLCD is working properly. The video processor generates and outputs a fault flag to initiate a corrective action if a fault is detected in the AMLCD and/or the path of the digital video stream.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for detecting a fault in a display system including an active matrix liquid crystal display (AMLCD), comprising: embedding fault detection data into a portion of a digital video stream that will not be displayed by the AMLCD, the AMLCD comprising: cascaded source and gate driver shift registers with associated return pulse circuitry; and a return pulse detector unit that detects return pulses from the shift registers; transmitting the digital video stream, with the embedded fault detection data, to the AMLCD; receiving detected fault detection data, detected by the AMLCD, from the AMLCD; comparing the embedded fault detection data with the received detected fault detection data detected by the AMLCD; receiving, from the return pulse detector, timing error data indicating whether a timing error occurred in the AMLCD, the timing error data generated by a timing and control circuit coupled to the AMLCD; and determining whether there is a fault in the AMLCD or in a path of the digital video stream based on results of the comparison and upon the received timing error data. 2. The method of claim 1 , wherein determining whether there is a fault includes detecting a difference between the detected fault detection data and the embedded fault detection data. 3. The method of claim 1 , further comprising outputting a signal to initiate corrective action responsive to determining that there is a fault in the AMLCD or in the path of the digital video stream. 4. The method of claim 1 , wherein determining whether there is a fault in the display system or the path of the digital video stream includes determining whether there is a difference between the detected fault detection data and the embedded encoded fault detection data which exceeds a threshold. 5. A display system, comprising: an active matrix liquid crystal display (AMLCD) comprising a carry over pixel (COP) detection unit that detects and returns COP data present within a plurality of digital video frames; and a fault detection system comprising: an encoder configured to encode and embed fault detection data associated with the detected COP data into a portion of a digital video frame that will not be displayed on the AMLCD, wherein the digital video frame is output, with the embedded encoded fault detection data, to the AMLCD as part of a digital video stream including the plurality of digital video frames; and a comparison unit incorporated within a processor, the comparison unit configured to receive captured fault detection data output by the display system and compare the captured fault detection data with the embedded encoded fault detection data to determine whether there is a difference between the captured fault detection data and the embedded encoded fault detection data, wherein the difference is indicative of a fault in the AMLCD or a path of the digital video frame. 6. The fault detection system of claim 5 , wherein the comparison unit outputs a signal to initiate correction action responsive to detecting the difference between the captured fault detection data and the embedded encoded fault detection data. 7. The fault detection system of claim 6 , wherein the comparison unit outputs the signal to initiate corrective action responsive to the difference between the captured fault detection data and the embedded encoded fault detection data exceeding a threshold. 8. The fault detection system of claim 5 , wherein the encoder embeds a sequence of encoded fault detection data across multiple digital video frames, and the comparison unit detects a difference between a sequence of fault detection data captured across the multiple digital video frames and the embedded sequence of encoded fault detection data. 9. The fault detection system of claim 5 , wherein the fault detection data is encoded and embedded, respectively, into each of the plurality of digital video frames, each respectively encoded and embedded fault detection data within respective digital video frames including a respectively unique COP. 10. The fault detection system of claim 9 , wherein the encoder uses pseudorandom binary sequence encoding to respectively encode each unique COP. 11. The fault detection system of claim 9 , wherein the respectively unique COP is embedded into a blanking interval of at least one of the plurality of digital video frames. 12. The fault detection system of claim 5 , wherein the comparison unit also analyzes timing error data received from the display system, wherein the timing error data indicates whether a timing error occurred in the display system. 13. A method for detecting a fault in a display system, comprising: providing an active matrix liquid crystal display (AMLCD) incorporated within the display system, the AMLCD comprising cascaded source and gate driver shift registers with associated return pulse circuitry and a return pulse detector unit that detects return pulses from the shift registers; embedding fault detection data into a portion of a digital video stream that will not be displayed by the AMLCD, wherein embedding the fault detection data includes embedding a sequence of fault detection data across multiple consecutive digital video frames of the digital video stream; transmitting the digital video stream, with the embedded fault detection data, to the AMLCD; receiving detected fault detection data, detected by the return pulse detector unit of the AMLCD, from the AMLCD; comparing the embedded fault detection data with the received detected fault detection data detected by the AMLCD; and determining whether there is a fault in the AMLCD or in a path of the digital video stream based on results of the comparison; and wherein: comparing the embedded fault detection data with the received detected fault detection data includes comparing the sequence of fault detection data embedded across the multiple consecutive digital video frames with a sequence of received detected fault detection data detected across the multiple consecutive digital video frames; and determining whether there is a fault in the display system or the path of the digital video stream includes detecting a difference between the sequence of fault detection data embedded across the multiple consecutive digital video frames and the sequence of received detected fault detection data detected across the multiple consecutive digital video frames. 14. The method of claim 13 , wherein determining whether there is a fault includes detecting a difference between the detected fault detection data and the embedded fault detection data. 15. The method of claim 13 , further comprising outputting a signal to initiate corrective action responsive to determining that there is a fault in the AMLCD or in the path of the digital video stream. 16. The method of claim 13 , wherein determining whether there is a fault in the display system or the path of the digital video stream includes determining whether there is a difference between the detected fault detection data and the embedded encoded fault detection data which exceeds a threshold. 17. A method for detecting a fault in a display system, comprising: providing an active matrix liquid crystal display (AMLCD) incorporated within the display system, the AMLCD comprising a carry over pixel (COP) detection unit that detects and returns COP data present within a plurality of digital video frames; embedding fault detection data into a portion of a digital video stream that will not be displayed by the AMLCD; transmitting the digital video stream, with the embedd

Assignees

Inventors

Classifications

  • using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

  • Test circuits or failure detection circuits included in a display system, as permanent part thereof · CPC title

  • Fault-tolerant or redundant circuits, or circuits in which repair of defects is prepared · CPC title

  • G09G3/006Primary

    Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays (testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309) · CPC title

  • G09G3/2096Primary

    Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167) · CPC title

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What does patent US10068509B2 cover?
A fault detection system is provided for a display system including an AMLCD. A video processor embeds encoded fault detection data within the digital video stream that is sent directly to the AMLCD. The fault detection data is embedded in such a manner that it is not displayed by the AMLCD. The fault detection data in the digital video stream received by the AMLCD is detected by the AMLCD and …
Who is the assignee on this patent?
L 3 Comm Corp
What technology area does this patent fall under?
Primary CPC classification G09G3/006. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Sep 04 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).