Memory chip, memory system, and method of accessing the memory chip

Patent metadata

Field	Value
Publication number	US-10067681-B2
Application number	US-201213427625-A
Country	US
Kind code	B2
Filing date	Mar 22, 2012
Priority date	May 26, 2011
Publication date	Sep 4, 2018
Grant date	Sep 4, 2018

Abstract

A memory chip, a memory system, and a method of accessing the memory chip. The memory chip includes a substrate, a first storage unit, and a second storage unit. The first storage unit includes a plurality of first memory cells may have a first storage capacity of 2n. The plurality of first memory cells may be configured to activate in response to a first selection signal. The second storage unit includes a plurality of second memory cells and may have a second storage capacity of 2n+1. The plurality of second memory cells may be configured to activate in response to a second selection signal.

First claim

What is claimed is:

1. A single memory chip comprising:
a substrate;
a first storage unit of the single memory chip, the first storage unit comprising a plurality of first memory cells having a first storage capacity of 2 n , wherein the plurality of first memory cells are configured to activate based on a first selection signal;
a second storage unit of the single memory chip, the second storage unit being physically separate from the first storage unit, the second storage unit comprising a plurality of second memory cells and having a second storage capacity of 2 n−1 , wherein the plurality of second memory cells are configured to activate based on a second selection signal; and
an interface unit configured selectively transmit data and address information received from an external device to a selected one of the first storage unit and the second storage unit in response to an externally received selection signal,
where the first storage unit and the second storage unit configured to store the received data at a location identified by the received address,
wherein the first storage unit and the second storage unit are disposed on and/or in the substrate, and
wherein n is a positive integer.

2. The single memory chip of claim 1 wherein the interface unit is configured to transmit first data, a first address, and a first control signal regarding the first storage unit from an external device, in response to the first selection signal, and to transmit second data, a second address, and a second control signal regarding the second storage unit from the external device, in response to the second selection signal.

3. The single memory chip of claim 2 , wherein the interface unit comprises:
a first input/output unit configured for transmitting or receiving the first data, the first address, and the first control signal regarding the first storage unit; and
a second input/output unit configured for transmitting or receiving the second data, the second address, and the second control signal regarding the second storage unit, and formed independently from the first input/output unit.

4. The single memory chip of claim 2 , wherein the interface unit comprises a common input/output unit for transmitting or receiving at least one of the group consisting of the first data, the first address, and the first control signal regarding the first storage unit, and transmitting or receiving at least one of the group consisting of the second data, the second address, and the second control signal regarding the second storage unit.

5. The single memory chip of claim 1 , wherein a type of each of the first memory cells is the same as the type of each of the second memory cells.

6. The single memory chip of claim 5 , wherein the plurality of first memory cells and the plurality of second memory cells comprise all of the memory cells of the single memory chip of the type.

7. The single memory chip of claim 1 , wherein a type of each of the first memory cells is different from the type of each of the second memory cells.

8. The single memory chip of claim 7 , wherein the type of each of the first and second memory cells is at least one of the group consisting of dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), and phase-change random access memory (PRAM), respectively.

9. The single memory chip of claim 1 , wherein a use of data stored in the first storage unit is the same as the use of data stored in the second storage unit.

10. The single memory chip of claim 1 , wherein a use of data stored in the first storage unit is different from the use of data stored in the second storage unit.

11. The single memory chip of claim 1 , wherein the sum of the first storage capacity of 2 n and the second storage capacity of 2 n−1 is not equal to an arbitrary standard capacity of 2 m , m being a positive integer greater than n.

Assignees

• Park Chul Sung
• Choi Joo Sun
• Samsung Electronics Co Ltd

Inventors

• Park Chul-Sung
• Choi Joo-Sun

Classifications

• G11C11/56

  using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency · CPC title

• G11C11/5607

  using magnetic storage elements · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title

• G11C11/5685

  using storage elements comprising metal oxide memory material, e.g. perovskites · CPC title

• G06F3/0688

  Non-volatile semiconductor memory arrays · CPC title