PLL with accelerated frequency lock

Patent metadata

Field	Value
Publication number	US-10063244-B1
Application number	US-201615284302-A
Country	US
Kind code	B1
Filing date	Oct 3, 2016
Priority date	Aug 25, 2009
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

First claim

What is claimed is:

1. A method of operation within in a phase-locked loop having a loop filter and voltage-controlled oscillator, the method comprising:
generating a feedback clock signal having a frequency according to a control voltage produced within the loop filter and supplied to the voltage-controlled oscillator;
detecting that the feedback clock signal cycles more or fewer than N times between transitions of a periodic reference signal, N being an integer greater than one; and
switchably coupling a first capacitive element to the loop filter for a predetermined interval in response to detecting that the feedback clock signal cycles more or fewer than N times between transitions of the periodic reference signal.

2. The method of claim 1 wherein generating the feedback clock signal having the frequency according to the control voltage comprises frequency-dividing an output clock of the voltage-controlled oscillator (VCO).

3. The method of claim 2 wherein frequency-dividing the VCO output clock comprises frequency-dividing the VCO output clock by an integer value that is varied over time to effect a fractional frequency division by M/N, M being a fractional value.

4. The method of claim 1 wherein detecting that the feedback clock signal cycles more or fewer than N times comprises counting transitions of the feedback clock over one or more cycles of the periodic reference signal.

5. The method of claim 1 wherein detecting that the feedback clock signal cycles more or fewer than N times comprises sampling the periodic reference signal in response to transitions of the feedback clock signal.

6. The method of claim 1 further comprising, prior to switchably coupling the first capacitive element to the loop filter, selectively charging or discharging the first capacitive element.

7. The method of claim 6 wherein selectively charging or discharging the first capacitive element comprises charging the first capacitive element in response to detecting that the feedback clock signal cycles more than N times and discharging the first capacitive element in response to detecting that the feedback clock signal cycles fewer than N times.

8. The method of claim 6 wherein selectively charging or discharging the first capacitive element comprises switchably coupling the first capacitive element to either a supply voltage node or a ground voltage node.

9. The method of claim 1 wherein switchably coupling the first capacitive element to the loop filter for the predetermined interval comprises switchably coupling the first capacitive element to the loop filter during a cycle of the periodic reference signal and then decoupling the first capacitive element from the loop filter during that same cycle of the periodic reference signal.

10. The method of claim 1 wherein the control voltage produced within the loop filter is an analog voltage, and wherein detecting that the feedback clock signal cycles more or fewer than N times between transitions of a periodic reference signal comprises detecting that the feedback signal cycles more or fewer than N times within a digital circuit.

11. The method of claim 1 further comprising detecting that the feedback clock signal cycles neither more nor fewer than N times between transitions of a periodic reference signal and, in response, refraining from switchably coupling the first capacitive element to the loop filter during at least one cycle of the periodic reference signal.

12. A phase-locked loop comprising:
a loop filter to produce a control voltage;
circuitry to generate a feedback clock signal having a frequency according to the control voltage produced within the loop filter;
a supplemental capacitive element; and
frequency detection circuitry to:
detect whether the feedback clock signal cycles more or fewer than N times between transitions of a periodic reference signal, N being an integer greater than one; and
switchably couple the supplemental capacitive element to the loop filter for a predetermined interval in response to detecting that the feedback clock signal cycles more or fewer than N times between transitions of the periodic reference signal.

13. The phase-locked loop of claim 12 wherein the circuitry to generate the feedback clock signal having the frequency according to the control voltage comprises circuitry to frequency-divide an output clock of the voltage-controlled oscillator (VCO).

14. The phase-locked loop of claim 13 wherein the circuitry to frequency-divide the VCO output clock comprises circuitry to divide the VCO output clock by an integer value that is varied over time to effect a fractional frequency division by M/N, M being a fractional value.

15. The phase-locked loop of claim 12 wherein the frequency detection circuitry to detect whether the feedback clock signal cycles more or fewer than N times comprises circuitry to count transitions of the feedback clock over one or more cycles of the periodic reference signal.

16. The phase-locked loop of claim 12 wherein the frequency detection circuitry to detect whether the feedback clock signal cycles more or fewer than N times comprises circuitry to sample the periodic reference signal in response to transitions of the feedback clock signal.

17. The phase-locked loop of claim 12 wherein the frequency detection circuit comprises circuitry to selectively charge or discharge the supplemental capacitive element prior to switchably coupling the supplemental capacitive element to the loop filter.

18. The phase-locked loop of claim 17 wherein the circuitry to selectively charge or discharge the supplemental capacitive element comprises circuitry to (i) charge the supplemental capacitive element in response to detecting that the feedback clock signal cycles more than N times, and (ii) discharge the supplemental capacitive element in response to detecting that the feedback clock signal cycles fewer than N times.

19. The phase-locked loop of claim 12 wherein the frequency detection circuitry to switchably couple the supplemental capacitive element to the loop filter for the predetermined interval comprises circuitry to switchably couple the supplemental capacitive element to the loop filter during a cycle of the periodic reference signal and then decouple the supplemental capacitive element from the loop filter during that same cycle of the periodic reference signal.

20. A phase-locked loop comprising:
a loop filter to produce a control voltage;
a supplemental capacitive element;
means for generating a feedback clock signal having a frequency according to the control voltage produced within the loop filter;
means for detecting whether the feedback clock signal cycles more or fewer than N times between transitions of a periodic reference signal, N being an integer greater than one; and
means for switchably couple the supplemental capacitive element to the loop filter for a predetermined interval in response to detecting that the feedback clock signal cycles more or fewer than N times between transitions of the periodic reference signal.

Assignees

• SiTime Coporation
• Sitime Corp

Inventors

• Perrott Michael H

Classifications

• H03L7/113

  using frequency discriminator · CPC title

• H03L7/091

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title

• H03L7/093

  using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) · CPC title

• H03H19/008 Primary

  with variable switch closing time · CPC title

• H03L7/087

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title