Providing an integrated directional coupler in a power amplifier
US-8981852-B2 · Mar 17, 2015 · US
US10063201B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10063201-B2 |
| Application number | US-201715820169-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 21, 2017 |
| Priority date | Oct 1, 2014 |
| Publication date | Aug 28, 2018 |
| Grant date | Aug 28, 2018 |
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A semiconductor integrated circuit includes a first pad provided on one end side of a first resistive element and one end side of a second resistive element externally provided, a second pad provided on a different end side of the first resistive element, a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided, an operation amplifier, a first signal line, wired between an output terminal of the operation amplifier and the first pad, a second signal line wired between an inverting input terminal of the operation amplifier and the second pad, a third signal line wired between the inverting input terminal of the operational amplifier and the third pad, a first ESD protection element, provided to the first signal line, a fourth signal line, through which a voltage signal of the first pad.
Opening claim text (preview).
What is claimed is: 1. A semiconductor integrated circuit comprising: a first pad provided on one end side of a first resistive element and one end side of a second resistive element externally provided; a second pad provided on a different end side of the first resistive element; a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided; an operation amplifier; a first signal line wired between an output terminal of the operation amplifier and the first pad; a second signal line wired between an inverting input terminal of the operation amplifier and the second pad; a third signal line wired between the inverting input terminal of the operational amplifier and the third pad; a first ESD (Electrostatic Discharge) protection element provided to the first signal line; a fourth signal line, through which a voltage signal of the first pad is transmitted, the fourth signal line being connected to the first pad, a first switch provided on the first signal line; a second switch provided on the second signal line; and a third switch provided on the third signal line, wherein a reference voltage is supplied to a non-inverting input terminal of the operation amplifier. 2. The semiconductor integrated circuit according to claim 1 , wherein an input current is supplied to the second pad and an input voltage is supplied to the third pad. 3. The semiconductor integrated circuit according to claim 1 , wherein at least one of the first switch, the second switch and the third switch is set by a register. 4. A variable gain amplifier comprising: the first resistive element; the second resistive element; the third resistive element; and the semiconductor integrated circuit according to claim 1 . 5. A semiconductor integrated circuit comprising: a first pad provided on one end side of a first resistive element and one end side of a second resistive element and one end side of a fourth resistive element and one end side of a fifth resistive element externally provided; a second pad provided on a different end side of the first resistive element; a third pad provided on a different end side of the second resistive element and one end side of a third resistive element externally provided; a fourth pad provided on a different end side of the fourth resistive element; a fifth pad provided on a different end side of the fifth resistive element and one end side of a sixth resistive element externally provided; an operation amplifier; a first signal line wired between an output terminal of the operation amplifier and the first pad; a second signal line wired between an inverting input terminal of the operation amplifier and the second pad; a third signal line wired between the inverting input terminal of the operational amplifier and the third pad; a fifth signal line wired between the inverting input terminal of the operational amplifier and the fourth pad; a sixth signal line wired between the inverting input terminal of the operational amplifier and the fifth pad; a first ESD (Electrostatic Discharge) protection element provided to the first signal line; a fourth signal line, through which a voltage signal of the first pad is transmitted, the fourth signal line being connected to the first pad, a first switch provided on the first signal line; a second switch provided on the second signal line; a third switch provided on the third signal line; a fourth switch provided on the fifth signal line; and a fifth switch provided on the sixth signal line, wherein a reference voltage is supplied to a non-inverting input terminal of the operation amplifier. 6. The semiconductor integrated circuit according to claim 5 , wherein a first input current is supplied to the second pad and a second input current is supplied to the fourth pad and a first input voltage is supplied to the third pad and a second input voltage is supplied to the fifth pad. 7. The semiconductor integrated circuit according to claim 5 , at least one of the first switch, the second switch, the third switch, the fourth switch, the fifth switch is set by a register. 8. A variable gain amplifier comprising: the first resistive element; the second resistive element; the third resistive element; the fourth resistive element; the fifth resistive element; the sixth resistive element; and the semiconductor integrated circuit according to claim 5 .
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