Carbon nanotube vacuum transistors

Patent metadata

Field	Value
Publication number	US-10062857-B2
Application number	US-201715594233-A
Country	US
Kind code	B2
Filing date	May 12, 2017
Priority date	Sep 2, 2015
Publication date	Aug 28, 2018
Grant date	Aug 28, 2018

Abstract

Vacuum transistors with carbon nanotube as the collector and/or emitter electrodes are provided. In one aspect, a method for forming a vacuum transistor includes the steps of: covering a substrate with an insulating layer; forming a back gate(s) in the insulating layer; depositing a gate dielectric over the back gate; forming a carbon nanotube layer on the gate dielectric; patterning the carbon nanotube layer to provide first/second portions thereof over first/second sides of the back gate, separated from one another by a gap G, which serve as emitter and collector electrodes; forming a vacuum channel in the gate dielectric; and forming metal contacts to the emitter and collector electrodes. Vacuum transistors are also provided.

First claim

What is claimed is:

1. A vacuum transistor, comprising:
a substrate covered with an insulating layer;
at least one back gate formed in the insulating layer;
a gate dielectric on the insulating layer over the at least one back gate;
a first carbon nanotube layer on the gate dielectric over a first side of the at least one back gate;
a second carbon nanotube layer on the gate dielectric over a second side of the at least one back gate, wherein the first carbon nanotube layer and the second carbon nanotube layer are separated from one another by a gap G over the at least one back gate, and wherein the first carbon nanotube layer serves as an emitter electrode of the vacuum transistor and the second carbon nanotube layer serves as a collector electrode of the vacuum transistor;
a vacuum channel in the gate dielectric over the at least one back gate, wherein the vacuum channel extends through the gate dielectric down to the at least one back gate, and wherein the vacuum channel has a width W that is greater than the gap G; and
metal contacts to the emitter electrode and to the collector electrode.

2. The vacuum transistor of claim 1 , wherein the insulating layer comprises silicon nitride or silicon dioxide.

3. The vacuum transistor of claim 1 , wherein the at least one back gate comprises a metal back gate.

4. The vacuum transistor of claim 1 , wherein a top surface of the at least one back gate is coplanar with a top surface of the insulating layer.

5. The vacuum transistor of claim 1 , wherein the at least one back gate is embedded in the insulating layer with a portion of the insulating layer separating the back gate from the substrate.

6. The vacuum transistor of claim 1 , wherein the first carbon nanotube layer and the second carbon nanotube layer each comprises single-wall carbon nanotubes.

7. The vacuum transistor of claim 1 , wherein the first carbon nanotube layer and the second carbon nanotube layer each comprises multi-wall carbon nanotubes.

8. The vacuum transistor of claim 1 , wherein the gap G is from about 5 nm to about 100 nm, and ranges therebetween.

9. The vacuum transistor of claim 1 , wherein the width W is from about 10 nm to about 150 nm, and ranges therebetween.

10. The vacuum transistor of claim 1 , wherein the metal contacts comprise a metal selected from the group consisting of: palladium, rhodium, titanium, copper, tungsten, and tantalum.

11. The vacuum transistor of claim 1 , wherein the at least one back gate and a portion of the insulating layer are exposed at a bottom of the vacuum channel.

12. A vacuum transistor, comprising:
a substrate covered with an insulating layer;
at least one back gate formed in the insulating layer;
a gate dielectric on the insulating layer over the at least one back gate;
a carbon nanotube layer on the gate dielectric over only a first side of the at least one back gate, wherein the carbon nanotube layer serves as an emitter electrode of the vacuum transistor;
a vacuum channel in the gate dielectric over the at least one back gate, wherein the vacuum channel extends through the gate dielectric down to the at least one back gate;
a first metal contact to the emitter electrode; and
a second metal contact on the gate dielectric over a second side of the at least one back gate, wherein the second metal contact serves as a collector electrode of the vacuum transistor, and wherein the carbon nanotube layer and the second metal contact are separated from one another by a gap G′ over the at least one back gate, wherein the vacuum channel has a width W′ that is greater than the gap G′.

13. The vacuum transistor of claim 12 , wherein the insulating layer comprises silicon nitride or silicon dioxide.

14. The vacuum transistor of claim 12 , wherein the at least one back gate comprises a metal back gate.

15. The vacuum transistor of claim 12 , wherein a top surface of the at least one back gate is coplanar with a top surface of the insulating layer.

16. The vacuum transistor of claim 12 , wherein the at least one back gate is embedded in the insulating layer with a portion of the insulating layer separating the back gate from the substrate.

17. The vacuum transistor of claim 12 , wherein the gap G′ is from about 5 nm to about 100 nm, and ranges therebetween.

18. The vacuum transistor of claim 12 , wherein the width W′ is from about 10 nm to about 150 nm, and ranges therebetween.

19. The vacuum transistor of claim 12 , wherein the carbon nanotube layer comprises either single-wall carbon nanotubes or multi-wall carbon nanotubes.

20. The vacuum transistor of claim 12 , wherein the carbon nanotube layer overlaps the at least one back gate, and wherein the carbon nanotube layer extends outward over the vacuum channel.

Assignees

• IBM

Inventors

• Cao Qing
• Cheng Kangguo
• Li Zhengwen
• Liu Fei

Classifications

• H01L51/0545

  Electricity · mapped topic

• H01L51/0562 Primary

  Electricity · mapped topic

• H01L51/0017

  Electricity · mapped topic

• H01L51/0048

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic